ICS1523
2
Video Clock Synthesizer with I C Programmable Delay
For the high logic level, the output transistor is off, so
the logic level is set by the ratio of R1 and R2 and the
voltage VAA. Generally, VAA will be equal to VDD.
Section 9 Output Termination
9.1 PECL Description
For logic low, the pull-down transistor turns on, pulling
the output voltage down to the low logic level.
Decoupling capacitor C1 should be a 0.01µF
high-frequency ceramic unit, and all power pins on the
ICS1523 should also be decoupled with similar
capacitors.
The ICS1523 PECL outputs consist of open-drain,
current-source, pull-down transistors. An external
resistor network permits complete flexibility of logic
levels and source impedance. This section describes
the design procedure to select the resistor values and
the pull-down current for these devices.
9.3 PECL Design Assumptions
9.2 PECL Output Structure
All referenced voltages in this application note are
positive and referenced to the GND pin of the chip.
However, negative logic levels can be generated by
level shifting, i.e. connecting the VDD pin of the device
to system ground and the GND pin to a negative
voltage.
The output stage and external circuitry are shown
below in Figure 9-1. The output devices are open-drain
pull-downs. The two output transistors switch
differentially, steering the current source
(programmable via RSET) from one output to the other.
All logic levels must be between GND and the lesser of
VAA and VDD. Then, nodal equations are written, with
resistances transformed into conductances.
Figure 9-1 PECL Termination Network
V
DD
RSET
V
CC
ICS1523
IREF (Pin 24)
CLK+ (Pin 21)
C
1
0.1µF
0.1µF
R
R
A
B
I
I
PECL
*
*
or CLK/2+ (Pin 23)
Destination
Device
R
A
PECL
CLK– (Pin 20)
R
B
or CLK/2– (Pin 22)
* Coaxial cable, microstrip, or stripline, with Z = R . Typically,
0
L
coaxial cable, microstrip, or stripline is not required if the distance
from the ICS1523 to the PECL load is short (that is, < 3 cm).
MDS 1523 Y
10
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