ICS1523
Video Clock Synthesizer with I
2
C Programmable Delay
Section 5
Register Set Details
Note 6 - ICP - Charge Pump Current
Register Conventions
0xY:Z = Register Index Y(hex), bit Z
0xY:Z~Q = Register Index Y(hex), bit Z to Q
Note 3- COAST - Charge Pump Enable/Disable
0x1
Bit 2~0
000
001
010
011
100
101
110
111
Charge Pump Current (µA)
1
2
4
8 (Typical Internal Filter Value)
16
32
64
Reserved
CP_Pol
00
x1
10
CPen
Charge Pump Enabled If...
COAST (Pin 5) = 1
Always Enabled (Default)
COAST (Pin 5) = 0
0x0:1~0
The COAST input can be used to disable the charge
pump during the vertical blanking interval if the input
HSYNC input changes frequency during this time. The
charge pump is asynchronously disabled and
synchronously re-enabled on the second input HSYNC
after the disable signal goes invalid. This pin can be
connected to VSYNC or pulled to either rail if unused.
Note 4 - LOCK/REF Function
Increasing the charge pump current makes the loop
respond faster, raising the loop bandwidth. The typical
value when using the internal loop filter is 011.
Note 7 - VCO Divider
0x1:bit 5,4
00
01
10
11
VCO Divider
2 (default)
4
8
16
EnPLS
0x0
bit 7~6
00
01
10
11
-
IN_SEL
0x7bit 7 LOCK/REF Output
-
-
-
0
0
PLL locked = 1 else 0
RESERVED
Post Schmitt trigger
HSYNC (pin 7) XOR
REF_Pol (0x0:2)
F
OSC
/ (OSC _DIV +2)
This is used to keep the VCO running at faster speeds
even when the output frequency is low.
VCO speed = Output Frequency * VCO Scaler
Note 8 - DPA Offset Ranges
0x5
bit 1-0
# of DPA Delay
Elements (d)
Clock Range (MHz)
0x4
bit 5-0
Min Max
Max. (h)
11
1
00
Note 5- CLK Output Divider
01
10
11
16
32
0F
1F
Reserved
48
24
160
80
0x6 bit 7,6
00
01
10
11
CLK Divider
1 (default)
2
4
8
64
3F
12
40
Using the DPA above 160 MHz is not recommended.
Set DPA_OS = 0 for speeds in excess of 160 MHz to
bypass the DPA.
SSTL_3 CLK Freq. = Output Freq. / CLK Divider
MDS 1523 Y
Integrated Circuit Systems
8
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Revision 110905
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