ICS1523
Video Clock Synthesizer with I
2
C Programmable Delay
4.1 Register Set Summary (continued)
Reg.
Index
0x6
Name
Output
Enables
Access
R/W
Bit Name
OE_Pck
OE_Tck
OE_P2
OE_T2
OE_F
Ck2_Inv
Out_Scl
Bit #
0
1
2
3
4
5
6-7
Reset
Value
0
0
0
0
0
0
0
Description
Output Enable for PECL CLK (Pins 20, 21)
0=High Z, 1=Enabled
Output Enable for STTL_3 CLK (Pin 17)
0=High Z, 1=Enabled
Output Enable for PECL CLK/2 (Pins 22, 23)
0=High Z, 1=Enabled
Output Enable for STTL_3 CLK/2 (Pin 16)
0=High Z, 1=Enabled)
Output Enable for STTL_3 FUNC Output (Pin15)
0=High Z, 1=Enabled
CLK/2 Invert (0=Not Inverted, 1= Inverted)
CLK Scaler (pin 17)
Bit 7, 6 = (00 = ÷ 1, 01 = ÷ 2, 10 = ÷ 4, 11 = ÷ 8)
See
Notes
0x7
Osc_Div
R/W
Osc_Div
0-6
In-Sel
0-6
7
0
1
Osc Divider modulus
See
Input Select
0=HSYNC Input, 1=Osc Divider
0x8
Reset
Write
DPA
PLL
0-3
4-7
x
x
Writing xAh resets DPA and loads working 0x5
Writing 5xh resets PLL and loads working 0x1- 0x3
0x10
Chip Ver
Read
Chip Ver
0-7
17
Chip Version 23 Dec (17h) as in 1523
0x11
Chip Rev
Read
Chip Rev
0-7
01
Initial value 01h. Value Increments with each all-layer change.
0x12
Rd_Reg
Read
Reserved
PLL_Lock
Reserved
0
1
2-7
N/A
N/A
0
Reserved
PLL Lock Status
0=Unlocked, 1=Locked
Reserved
MDS 1523 Y
Integrated Circuit Systems
7
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Revision 110905
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