P R E L I M I N A RY I N F O R M AT I O N
ICS1493-17
Clock Synthesizer for Portable Systems
Byte 1: Control Register
Bit
7
6
@Pup
1
1
Name
REF
37SS
Description
REF Output Enable
0 = Disable, Output pulled low, 1 = Enable
37SS Output Enable
0 = Disable, Output pulled low, corresponding PLL shut off.
1 = Enable
48M Output Enable
0 = Disable, Output pulled low, 1 = Enable
22/24M Clock Output Enable
0 = Disable, Output pulled low, 1 = Enable
22M Output Enable
0 = Disable, Output pulled low and corresponding PLL off,
1 = Enable
Reserved
Reserved
22/24M Clock Select
1 = 24.576 MHz, 0 = 22.5792 MHz
5
4
3
1
1
0
48M
22/24M
22M
2
1
0
1
1
1
Reserved
Reserved
22/24M SEL
Byte 2: Control Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
1
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
SS Table
SS Table
SS Table
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Bit 2:0=000: No Spread
Bit 2:0=001: -0.5% Spread
Bit 2:0=010:-1.0% Spread
Bit 2:0=011: No Spread
Bit 2:0=100: -2.0% Spread
Bit 2:0=101: No Spread
Bit 2:0=110: -3.0% Spread
Bit 2:0=111: No Spread
MDS 1493-17 A
Integrated Circuit Systems
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9
525 Ra ce Stree t, Sa n Jose, CA 951 26
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Revision 101005
te l (4 08) 297 -1201
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w w w. i c s t . c o m
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
