IC61LV6432
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-166
-133
-117
Symbol
tKC
tKH
Parameter
Cycle Time
Clock High Time
Clock Low Time
Min. Max Min. Max. Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
6
—
—
—
5
7.5
2.8
2.8
—
1.5
0
1.5
—
0
—
—
—
5
8.5
3
—
—
—
5
2.4
2.4
—
1.5
0
1.5
—
0
tKL
3
tKQ
Clock Access Time
—
1.5
0
1.5
—
0
(3)
tKQX
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Disable to Output Invalid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
Address Status Setup Time
Chip Enable Setup Time
Address Hold Time
—
—
5
—
—
5
—
—
6
(3,4)
tKQLZ
(3,4)
tKQHZ
tOEQ
5
5
5
(3)
tOEQX
—
—
3
—
—
3
—
—
4
(3,4)
tOELZ
0
0
0
(3,4)
tOEHZ
—
2.5
2.5
2.5
2.5
2.5
2.5
2
—
2.5
2.5
2.5
2.5
2.5
2.5
2
—
2.5
2.5
2.5
2.5
2.5
2.5
2
tAS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tSS
tCES
tAH
tSH
Address Status Hold Time
Chip Enable Hold Time
ZZ Standby
tCEH
(5)
tZZS
(6)
tZZREC
ZZRecovery
2
2
2
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. ADVANCEINFORMATIONONLY.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
5. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
6. ADSC and ADSP must not be asserted for at least two cycles after leaving ZZ state.
Integrated Circuit Solution Inc.
17
SSR005-0A 02/02/2004
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
