IC42S32200
IC42S32200L
6
Concurrent Auto Precharge
An access command (READ or WRITE) to another bank while an access command with auto precharge enabled
is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE.
ICSI SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO
PRECHARGE occurs are defined below.
READ with Auto Precharge
· Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n,
CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is regis-tered.
READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
BANK n
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
t
Idle
t
RP - BANK
n
RP - BANKm
Precharge
Internal
States
Page Active
READ with Burst of 4
BANK m
BANK n,
COLa
BANK m,
COLd
ADDRESS
DQ
DOUT
DOUT
DOUT
DOUT
a
a + 1
d
d + 1
CAS Latency = 3 (BANKn)
CAS Latency = 3 (BANKm)
NOTE: DQM is LOW.
DON T CARE
· Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n
when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to bank m is registered.
READ With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
BANK n
Page
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t
Idle
WR - BANK m
Active
t
RP -BANK
n
Internal
States
Write-Back
WRITE with Burst of 4
BANK m
BANK n,
COLa
BANK m,
COLd
ADDRESS
1
DQM
D
OUT
DIN
d
D
d + 1
IN
D
d + 2
IN
DIN
d + 3
DQ
a
CAS Latency = 3 (BANKn)
OUT-a+1 from contending with D IN-d at T4.
NOTE: 1. DQM is HIGH at T2 to prevent
D
DON’T CARE
Integrated Circuit Solution Inc.
13
DR036-0D 02/04/2005
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
