IC42S32200
IC42S32200L
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Bank,
Row
Bank,
Col A
Bank(s)
ADDRESS
tRP
READ A
NOP
NOP
NOP
COMMAND
Activate
NOP
NOP
Precharge
NOP
CAS# latency=2
DOUT A
DOUT A
2
DOUT A
DOUT A
3
0
1
t
, DQ s
CK2
CAS# latency=3
, DQ
DOUT A
DOUT A
2
DOUT A
DOUT A
3
0
1
t
s
CK3
Read to Precharge (CAS#Latency =2,3)
5
Write command
(RAS#=”H”,CAS#=”L”,WE#=”L”,BS =Bank,A10 =”L”,A0-A7 =Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active
bank.The bank must be active for at least tRCD(min.)before the Write command is issued.During write bursts,
the first valid data-in element will be registered coincident with the Write command.Subsequent data elements
will be registered on each successive positive clock edge (refer to the following figure).The DQs remain with high-
impedance at the end of the burst unless another command is initiated.The burst length and burst sequence are
determined by the mode register,which is already programmed.A full-page burst will continue until terminated (at
the end of the page it will wrap to column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
NOP
WR
I
NOP
NOP
NOP
NOP
DIN A
DIN A
DIN A
DIN A
3
don’t care
DQ0 - DQ3
0
1
2
The first data element and the write
Extra data is masked.
are registered on the same clock edge.
Burst Write Operation (Burst Length =4,CAS#Latency =2,3)
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write, BankPrecharge/
PrechargeAll,or Read command before the end of the burst length.An interrupt coming from Write command can
occur on any clock cycle following the previous Write command (refer to the following figure).
Integrated Circuit Solution Inc.
11
DR036-0D 02/04/2005
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
