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85301AGL 参数 Datasheet PDF下载

85301AGL图片预览
型号: 85301AGL
PDF下载: 下载PDF文件 查看货源
内容描述: 2 : 1差分至LVPECL多路复用器 [2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER]
分类和应用: 复用器
文件页数/大小: 19 页 / 299 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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ICS85301  
2:1  
DIFFERENTIAL-TO-LVPECL MULTIPLEXER  
Integrated  
Circuit  
Systems, Inc.  
RECOMMENDATIONS FOR UNUSED INPUT PINS  
INPUTS:  
PCLK/nPCLK INPUT:  
For applications not requiring the use of a differential input,  
both the PCLK and nPCLK pins can be left floating. Though  
not required, but for additional protection, a 1kΩ resistor can  
be tied from PCLK to ground.  
TERMINATION FOR 3.3V LVPECL OUTPUT  
The clock layout topology shown below is a typical termi- ance techniques should be used to maximize operating  
nation for LVPECL outputs. The two different layouts men- frequency and minimize signal distortion. Figures 3A and  
tioned are recommended only as guidelines.  
3B show two different layouts which are recommended only  
as guidelines. Other suitable clock layouts may exist and it  
FOUT and nFOUT are low impedance follower outputs that would be recommended that the board designers simulate  
generate ECL/LVPECL compatible outputs. Therefore, ter- to guarantee compatibility across all printed circuit and clock  
minating resistors (DC current path to ground) or current component process variations.  
sources must be used for functionality. These outputs are  
designed to drive 50Ω transmission lines. Matched imped-  
3.3V  
Z
o = 50Ω  
125Ω  
125Ω  
FOUT  
FIN  
Zo = 50Ω  
Zo = 50Ω  
Zo = 50Ω  
FOUT  
FIN  
50Ω  
50Ω  
VCC - 2V  
1
RTT =  
Zo  
RTT  
((VOH + VOL) / (VCC – 2)) – 2  
84Ω  
84Ω  
FIGURE 3A. LVPECL OUTPUTTERMINATION  
FIGURE 3B. LVPECL OUTPUTT ERMINATION  
85301AK  
www.icst.com/products/hiperclocks.html  
REV.A JANUARY 16, 2006  
10  
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