ICS840002I
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
LAYOUT GUIDELINE
and C2=22pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted
for optimizing frequency accuracy. 1KΩ pullup or pulldown re-
sistors can be used for the logic control input pins.
Figure 3 shows a schematic example of the ICS840002I. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18
pF parallel resonant 26.5625MHz crystal is used.The C1=22pF
Logic Control Input Examples
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
R2
33
Zo = 50 Ohm
RU1
1K
RU2
Not Install
VDD
To Logic
Input
pins
To Logic
Input
pins
U1
LVCMOS
RD1
Not Install
RD2
1K
1
16
15
14
13
12
11
10
9
FSEL0
XTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
FSEL1
GND
GND
Q0
Q1
VDDO
XTAL_I N
XTAL_OUT
2
3
4
5
6
7
8
VDD
VDD
VDDA
R3
VDD
R1
10
C3
10uF
100
C4
0.01u
C6
0.1u
Zo = 50 Ohm
C5
0.1u
ICS840002i
R4
100
XTAL2
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
tied to ground.
LVCMOS
C2
22pF
X1
XTAL1
Optional Termination
C1
22pF
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
FIGURE 3. ICS840002I SCHEMATIC EXAMPLE
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
10
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
