ICS601-25
L
OW
P
HASE
N
OISE
1
TO
5 C
LOCK
M
ULTIPLIER
Description
The ICS601-25 is a low-cost, low phase noise, high
performance clock synthesizer for applications which
require low phase noise, low jitter, and low skew fanout.
It is ICS’ lowest phase noise multiplier, and also the
lowest CMOS part in the industry. Using ICS’ patented
analong and digital Phase Locked Loop (PLL)
techniques, the chip accepts a 10-27 MHz crystal or
clock input, and produces output clocks up to 156 MHz.
Features
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Packaged in 20-pin SSOP
Uses fundamental 10 - 27 MHz crystal or clock
Output clocks up to 156 MHz
Low phase noise: -132 dBc/Hz at 10 kHz
Five low skew (<250 ps) outputs
Low jitter - 18 ps one sigma at 125 MHz
Full swing CMOS outputs with 25 mA drive capability
at TTL levels
Powerdown mode lowers power consumption
Advanced, low power, sub-micron CMOS process
Industrial temperature version available
Available in Pb (lead) free package
Operating voltage of 3.3 V
Block Diagram
VDD
5
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLK1
CLK2
X1/ICLK
Crystal or
clock input
Crystal
Oscillator
X2
VCO
Divide
CLK3
CLK4
CLK5
ROM Based
Multipliers
4
S3:0
3
GND
PD
MDS 601-25 C
I n t e gra te d C i r c u i t S y s t e m s
●
1
525 Race Stre et, San Jo se, CA 9 5126
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Revision 071505
te l (40 8) 2 97-12 01
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w w w. i c st . c o m
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
