ICS556-04
L
OW
S
KEW
1
TO
4 C
LOCK
B
UFFER
Pin Assignment
VDD
X 1 / I CL K
X2
GN D
1
2
3
4
8
7
6
5
Q4
Q3
Q2
Q1
8 - p i n ( 1 5 0 mi l ) S OI C
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
VDD
X1/ICLK
X2
GND
Q1
Q2
Q3
Q4
Pin
Type
Power
Input
Input
Power
Output
Output
Output
Output
Pin Description
Connect to +2.5 V, +3.3 V or +5.0 V.
Crystal or clock input (5 V tolerant input). Connect to 5 to 27 MHz input.
Connect to a fundamental mode crystal. Leave open for clock input.
Connect to ground.
Clock Output 1.
Clock Output 2.
Clock Output 3.
Clock Output 3.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01
µF
should be connected between VDD on pin 1 and GND on pin 4, as close to the device as possible. A 33Ω series
terminating resistor may be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the ICS556-04 is capable of, careful attention must be paid to board layout.
Essentially, all four outputs must have identical terminations, identical loads, and identical trace geometries. If not,
the output skew will be degraded. For example, using a 30Ω series termination on one output (with 33Ω on the
others) will cause at least 15 ps of skew.
Crystal Information
The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors
should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these
capacitors is given by the following equation:
Crystal caps (pF) = (CL - 6) x 2
In the equation, CL is the crystal load capacitance. So, for a crystal with a 16 pF load capacitance, two 20 pF [(16-6)
x 2] capacitors should be used.
MDS 556-04 C
In te grated Circuit Systems
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ICS [ INTEGRATED CIRCUIT SYSTEMS ]
