Integrated
Circuit
Systems, Inc.
ICS843-75
75MH
Z
, LVCMOS, LVPECL
D
UAL
O
UTPUT
O
SCILLATOR
crystal, see the application note,
Crystal Timing Budget
and Accuracy for FemtoClock™
.
F
REQUENCY
S
TABILITY
The table shown below provides a basic guideline in se-
lecting the proper quartz crystal that meets a timing budget
of ±100ppm. For more information on selecting the proper
Parameter
Frequency Tolerance
Frequency Stability
Aging for 10 Years
Accuracy of ICS Oscillator
Load Capacitance Accuracy
Total Overall Timing Error
Typical
±30
±30
Units
ppm
ppm
pp m
ppm
pp m
ppm
±15
±10
±3
±88
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
drive 50Ω transmission lines.Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 2A and 2B
show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
Z
o
= 50Ω
FOUT
FIN
3.3V
125Ω
Z
o
= 50Ω
125Ω
Z
o
= 50Ω
50Ω
1
RTT =
Z
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
o
50Ω
V
CC
- 2V
RTT
FOUT
FIN
Z
o
= 50Ω
84Ω
84Ω
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
843AG-75
www.icst.com/products/hiperclocks.html
7
REV. A JANUARY 9, 2006
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
