Integrated
Circuit
Systems, Inc.
ICS840002-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
Type
Input
Input
Input
Input
Input
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Description
Frequency select pin. LVCMOS/LVTTL interface levels.
Selects between the cr ystal or TEST_CLK inputs as the PLL reference
source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
Single-ended LVCMOS/LVTTL clock input.
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing active outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
When HIGH, the PLL is bypassed and the output frequency =
reference clock frequency/N output divider.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Cr ystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Output supply pin.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
Name
F_SEL0
nXTAL_SEL
TEST_CLK
OE
MR
6
7
8
9,
10
11
12, 13
14, 15
16
nPLL_SEL
V
DDA
V
DD
XTAL_OUT,
XTAL_IN
V
DDO
Q1, Q0
GND
F_SEL1
Input
Power
Power
Input
Power
Output
Power
Input
Pulldown
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
3.3V±5%
2.5V±5%
14
16
Test Conditions
Minimum
Typical
4
8
51
51
17
21
21
25
Maximum
Units
pF
pF
kΩ
kΩ
Ω
Ω
840002AG-01
www.icst.com/products/hiperclocks.html
2
REV. B JANUARY 13, 2006
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
