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40002A01 参数 Datasheet PDF下载

40002A01图片预览
型号: 40002A01
PDF下载: 下载PDF文件 查看货源
内容描述: FEMTOCLOCKS⑩ CRYSTAL -TO LVCMOS / LVTTL频率合成器 [FEMTOCLOCKS⑩ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER]
分类和应用:
文件页数/大小: 12 页 / 197 K
品牌: ICS [ INTEGRATED CIRCUIT SYSTEMS ]
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Integrated
Circuit
Systems, Inc.
ICS840002-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
R
ECOMMENDATIONS FOR
U
NUSED
I
NPUT AND
O
UTPUT
P
INS
I
NPUTS
:
O
UTPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
TEST_CLK I
NPUT
:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the TEST_CLK to
ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
L
AYOUT
G
UIDELINE
Figure 3
shows a schematic example of the ICS840002-01. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18
pF parallel resonant 25MHz crystal is used. The C1=22pF and
Logic Control Input Examples
VDD
C2=22pF are recommended for frequency accuracy. For differ-
ent board layout, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. 1KΩ pullup or pulldown resis-
tors can be used for the logic control input pins.
Set Logic
Input to
'1'
RU1
1K
VDD
Set Logic
Input to
'0'
RU2
Not Install
VDD
R2
33
Zo = 50 Ohm
To Logic
Input
pins
RD1
Not Install
RD2
1K
To Logic
Input
pins
U1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Zo = 50 Ohm
C5
0.1u
XTAL2
R4
100
LVCMOS
VDD
R1
10
VDDA
C3
10uF
C4
0.01u
C6
0.1u
FSEL0
XTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
VDD
FSEL1
GND
GND
Q0
Q1
VDDO
XTAL_IN
XTAL_OUT
VDD
R3
100
ICS840002-01
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
tied to ground.
LVCMOS
C2
22pF
X1
XTAL1
Optional Termination
C1
22pF
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
F
IGURE
3. ICS840002-01 S
CHEMATIC
E
XAMPLE
840002AG-01
www.icst.com/products/hiperclocks.html
8
REV. B JANUARY 13, 2006