欢迎访问ic37.com |
会员登录 免费注册
发布采购

X25642FV 参数 Datasheet PDF下载

X25642FV图片预览
型号: X25642FV
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的SPI串行E2PROM与块锁保护 [Advanced SPI Serial E2PROM with Block Lock Protection]
分类和应用: 可编程只读存储器
文件页数/大小: 16 页 / 135 K
品牌: ICMIC [ IC MICROSYSTEMS ]
 浏览型号X25642FV的Datasheet PDF文件第1页浏览型号X25642FV的Datasheet PDF文件第2页浏览型号X25642FV的Datasheet PDF文件第3页浏览型号X25642FV的Datasheet PDF文件第4页浏览型号X25642FV的Datasheet PDF文件第6页浏览型号X25642FV的Datasheet PDF文件第7页浏览型号X25642FV的Datasheet PDF文件第8页浏览型号X25642FV的Datasheet PDF文件第9页  
X25642  
Data Protection  
Operational Notes  
The following circuitry has been included to prevent in-  
advertent writes:  
The X25642 powers-up in the following state:  
• The device is in the low power standby state.  
• The “write enable” latch is reset upon power-up.  
• A HIGH to LOW transition on CS is required to enter  
an active state and receive an instruction.  
• A WREN instruction must be issued to set the “write  
enable” latch.  
• SO pin is high impedance.  
• CS must come HIGH at the proper clock count in or-  
der to start a write cycle.  
• The “write enable” latch is reset.  
2
Figure 1. Read E PROM Array Operation Sequence  
CS  
0
1
2
3
4
5
6
7
8
9
10  
20 21 22 23 24 25 26 27 28 29 30  
SCK  
SI  
INSTRUCTION  
16 BIT ADDRESS  
15 14 13  
3
2
1
0
DATA OUT  
HIGH IMPEDANCE  
7
6
5
4
3
2
1
0
SO  
MSB  
3132 ILL F03.1  
Figure 2. Read Status Register Operation Sequence  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14  
SCK  
SI  
INSTRUCTION  
DATA OUT  
HIGH IMPEDANCE  
7
MSB  
6
5
4
3
2
1
0
SO  
3132 ILL F04  
5