X25642
Data Protection
Operational Notes
The following circuitry has been included to prevent in-
advertent writes:
The X25642 powers-up in the following state:
• The device is in the low power standby state.
• The “write enable” latch is reset upon power-up.
• A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
• A WREN instruction must be issued to set the “write
enable” latch.
• SO pin is high impedance.
• CS must come HIGH at the proper clock count in or-
der to start a write cycle.
• The “write enable” latch is reset.
2
Figure 1. Read E PROM Array Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
INSTRUCTION
16 BIT ADDRESS
15 14 13
3
2
1
0
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
3132 ILL F03.1
Figure 2. Read Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
SI
INSTRUCTION
DATA OUT
HIGH IMPEDANCE
7
MSB
6
5
4
3
2
1
0
SO
3132 ILL F04
5
ICMIC [ IC MICROSYSTEMS ]
