欢迎访问ic37.com |
会员登录 免费注册
发布采购

X25642FV 参数 Datasheet PDF下载

X25642FV图片预览
型号: X25642FV
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的SPI串行E2PROM与块锁保护 [Advanced SPI Serial E2PROM with Block Lock Protection]
分类和应用: 可编程只读存储器
文件页数/大小: 16 页 / 135 K
品牌: ICMIC [ IC MICROSYSTEMS ]
 浏览型号X25642FV的Datasheet PDF文件第1页浏览型号X25642FV的Datasheet PDF文件第3页浏览型号X25642FV的Datasheet PDF文件第4页浏览型号X25642FV的Datasheet PDF文件第5页浏览型号X25642FV的Datasheet PDF文件第6页浏览型号X25642FV的Datasheet PDF文件第7页浏览型号X25642FV的Datasheet PDF文件第8页浏览型号X25642FV的Datasheet PDF文件第9页  
X25642  
X25642 status register. If the internal write cycle has  
already been initiated, WP going LOW will have no  
affect on a write.  
PIN DESCRIPTIONS  
Serial Output (SO)  
SO is a push/pull serial data output pin. During a read  
cycle, data is shifted out on this pin. Data is clocked  
out by the falling edge of the serial clock.  
The WP pin function is blocked when the WPEN bit in  
the status register is “0”. This allows the user to install  
the X25642 in a system with WP pin grounded and still  
be able to write to the status register.The WP pin func-  
tions will be enabled when the WPEN bit is set “1”.  
Serial Input (SI)  
SI is the serial data input pin. All opcodes, byte  
addresses, and data to be written to the memory are  
input on this pin. Data is latched by the rising edge of  
the serial clock.  
Hold (HOLD)  
HOLD is used in conjunction with the CS pin to select  
the device. Once the part is selected and a serial  
sequence is underway, HOLD may be used to pause  
Serial Clock (SCK)  
The Serial Clock controls the serial bus timing for data  
input and output. Opcodes, addresses, or data present  
on the SI pin are latched on the rising edge of the  
clock input, while data on the SO pin change after the  
falling edge of the clock input.  
PIN CONFIGURATION  
Not to Scale  
SOIC/DIP  
CS  
SO  
WP  
1
2
3
4
8
7
6
5
V
CC  
HOLD  
SCK  
SI  
Chip Select (CS)  
.197"  
SOIC  
Only  
X25642  
When CS is HIGH, the X25642 is deselected and the  
SO output pin is at high impedance and unless an  
internal write operation is underway, the X25642 will be  
in the standby power mode. CS LOW enables the  
X25642, placing it in the active power mode. It should  
be noted that after power-up, a HIGH to LOW transition  
on CS is required prior to the start of any operation.  
V
SS  
.244"  
SOIC  
NC  
CS*  
CS*  
SO  
1
2
3
4
5
6
7
14  
13  
12  
NC  
NC  
Write Protect (WP)  
V
CC  
.345"  
X25642 11  
HOLD  
SCK  
SI  
When WP is LOW and the nonvolatile bit WPEN is “1”,  
nonvolatile writes to the X25642 status register are  
disabled, but the part otherwise functions normally.  
When WP is held HIGH, all functions, including  
nonvolatile writes operate normally. WP going LOW  
while CS is still LOW will interrupt a write to the  
WP  
10  
9
V
SS  
NC  
8
NC  
.244"  
TSSOP  
PIN NAMES  
20  
NC  
NC  
CS  
NC  
SO  
NC  
NC  
WP  
1
Symbol  
CS  
Description  
Chip Select Input  
2
19  
V
CC  
3
18  
NC  
4
17  
SO  
Serial Output  
Serial Input  
HOLD  
NC  
5
16  
SI  
.300"  
X25642  
6
15  
NC  
SCK  
WP  
Serial Clock Input  
Write Protect Input  
Ground  
7
14  
SCK  
SI  
8
13  
V
SS  
NC  
NC  
VSS  
9
12  
NC  
VCC  
HOLD  
NC  
Supply Voltage  
Hold Input  
10  
11  
NC  
.252"  
No Connect  
3132 ILL F02.5  
7037 FRM T01  
* Pin 2 and Pin 3 are internally connected. Only one CS needs to  
be connected externally.  
2