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X25160SI 参数 Datasheet PDF下载

X25160SI图片预览
型号: X25160SI
PDF下载: 下载PDF文件 查看货源
内容描述: SPI串行E2PROM带座LockTM保护 [SPI Serial E2PROM With Block LockTM Protection]
分类和应用: 可编程只读存储器
文件页数/大小: 15 页 / 127 K
品牌: ICMIC [ IC MICROSYSTEMS ]
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X25160  
PRINCIPLES OF OPERATION  
Status Register  
The X25160 is a 2K x 8 E2PROM designed to interface  
directly with the synchronous serial peripheral interface  
(SPI) of many popular microcontroller families.  
The RDSR instruction provides access to the status  
register. The status register may be read at any time,  
even during a write cycle. The status register is format-  
ted as follows:  
The X25160 contains an 8-bit instruction register. It is  
accessed via the SI input, with data being clocked in on  
therisingSCK. CS mustbeLOWandtheHOLD andWP  
inputs must be HIGH during the entire operation. The  
WP input is “Don’t Care” if WPEN is set “0”.  
7
6
5
4
3
2
1
0
WPEN  
X
X
X
BP1  
BP0 WEL WIP  
3064 PGM T02  
WPEN, BP0 and BP1 are set by the WRSR instruction.  
WEL and WIP are read-only and automatically set by  
other operations.  
Table 1 contains a list of the instructions and their  
opcodes. All instructions, addresses and data are trans-  
ferred MSB first.  
The Write-In-Process (WIP) bit indicates whether the  
X25160 is busy with a write operation. When set to a “1”,  
a write is in progress, when set to a “0”, no write is in  
progress. During a write, all other bits are set to “1”.  
DatainputissampledonthefirstrisingedgeofSCKafter  
CS goes LOW. SCK is static, allowing the user to stop  
the clock and then resume operations. If the clock line is  
shared with other peripheral devices on the SPI bus, the  
usercanasserttheHOLD inputtoplacetheX25160into  
aPAUSEcondition.AfterreleasingHOLD,theX25160  
will resume operation from the point when HOLD was  
first asserted.  
The Write Enable Latch (WEL) bit indicates the status of  
thewriteenablelatch.Whensettoa1”,thelatchisset,  
when set to a “0”, the latch is reset.  
The Block Protect (BP0 and BP1) bits are nonvolatile  
and allow the user to select one of four levels of protec-  
tion. The X25160 is divided into four 4096-bit segments.  
One, two, or all four of the segments may be protected.  
That is, the user may read the segments but will be  
unabletoalter(write)datawithintheselectedsegments.  
The partitioning is controlled as illustrated below.  
Write Enable Latch  
The X25160 contains a “write enable” latch. This latch  
must be SET before a write operation will be completed  
internally. The WREN instruction will set the latch and  
the WRDI instruction will reset the latch. This latch is  
automatically reset upon a power-up condition and after  
the completion of a byte, page, or status register write  
cycle.  
Status Register Bits  
Array Addresses  
Protected  
BP1  
BP0  
0
0
1
1
0
1
0
1
None  
$0600–$07FF  
$0400–$07FF  
$0000–$07FF  
3064 PGM T03  
Table 1. Instruction Set  
Instruction Name  
WREN  
Instruction Format*  
0000 0110  
Operation  
Set the Write Enable Latch (Enable Write Operations)  
Reset the Write Enable Latch (Disable Write Operations)  
Read Status Register  
WRDI  
0000 0100  
RDSR  
0000 0101  
WRSR  
0000 0001  
Write Status Register  
Read Data from Memory Array beginning at selected  
address  
READ  
0000 0011  
0000 0010  
Write Data to Memory Array beginning at Selected Address  
(1 to 32 Bytes)  
WRITE  
3064 PGM T04  
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.  
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