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X24C04FS14 参数 Datasheet PDF下载

X24C04FS14图片预览
型号: X24C04FS14
PDF下载: 下载PDF文件 查看货源
内容描述: 串行E2PROM [Serial E2PROM]
分类和应用: 可编程只读存储器
文件页数/大小: 18 页 / 393 K
品牌: ICMIC [ IC MICROSYSTEMS ]
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X24C04  
DEVICE ADDRESSING  
The last bit of the slave address defines the operation to be  
performed. When set to one a read operation is  
Following a start condition the master must output the  
address of the slave it is accessing. The most significant  
selected, when set to zero a write operation is selected.  
four bits of the slave are the device type identifier (see  
Figure 4). For the X24C04 this is fixed as 1010[B].  
Following the start condition, the X24C04 monitors the  
SDA bus comparing the slave address being transmitted  
with its slave address (device type and state of A1  
Figure 4. Slave Address  
and A2 inputs). Upon a correct compare the X24C04  
outputs an acknowledge on the SDA line. Depending on the  
state of the R/W bit, the X24C04 will execute a read  
HIGH  
ORDER  
DEVICE WORD  
ADDRESS ADDRESS  
or write operation.  
DEVICE TYPE  
IDENTIFIER  
WRITE OPERATIONS  
1
0
1
0
A2  
A1  
A0 R/W  
Byte Write  
For a write operation, the X24C04 requires a second  
address field. This address field is the word address,  
3839 FHD F09  
comprised of eight bits, providing access to any one of the  
512 words of memory. Upon receipt of the word address  
the X24C04 responds with an acknowledge, and awaits the  
next eight bits of data, again responding with an  
The next two significant bits address a particular device. A  
system could have up to four X24C04 devices on the  
bus (see Figure 10). The four addresses are defined by the  
acknowledge. The master then terminates the transfer by  
generating a stop condition, at which time the X24C04  
state of the A1 and A2 inputs.  
begins the internal write cycle to the nonvolatile memory.  
While the internal write cycle is in progress the X24C04  
The next bit of the slave address is an extension of the  
array’s address and is concatenated with the eight bits  
inputs are disabled, and the device will not respond to any  
requests from the master. Refer to Figure 5 for the  
address, acknowledge and data transfer sequence.  
of address in the word address field, providing direct access  
to the whole 512 x 8 array.  
Figure 5. Byte Write  
S
T
S
T
SLAVE  
WORD  
ADDRESS  
A
BUS ACTIVITY:  
ADDRESS  
DATA  
R
T
MASTER  
O
P
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:  
X24C04  
3839 FHD F10  
5