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X24012S 参数 Datasheet PDF下载

X24012S图片预览
型号: X24012S
PDF下载: 下载PDF文件 查看货源
内容描述: 串行E2PROM [Serial E2PROM]
分类和应用: 可编程只读存储器
文件页数/大小: 14 页 / 271 K
品牌: ICMIC [ IC MICROSYSTEMS ]
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X24012  
The data output is sequential, with the data from address n  
followed by the data from n + 1. The address counter  
Sequential Read  
Sequential Read can be initiated as either a current  
address read or random access read. The first word is  
for read operations increments all address bits, allowing the  
entire memory contents to be serially read during  
transmitted as with the other modes, however, the  
master now responds with an acknowledge, indicating it  
one operation. At the end of the address space (address 127),  
the counter “rolls over” to address 0 and the  
requires additional data. The X24012 continues to out- put  
data for each acknowledge received. The read  
X24012 continues to output data for each acknowledge  
received. Refer to Figure 9 for the address, acknowledge  
and data transfer sequence.  
operation is terminated by the master, by not responding with  
an acknowledge and by issuing a stop condition.  
Figure 9. Sequential Read  
S
T
SLAVE  
ADDRESS  
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:  
MASTER  
O
P
SDA LINE  
P
A
C
K
BUS ACTIVITY:  
X24012  
DATA n  
DATA n+1  
DATA n+2  
DATA n+x  
3847 FHD F14  
Figure 10. Typical System Configuration  
V
CC  
SDA  
SCL  
MASTER  
SLAVE  
SLAVE  
TRANSMITTER/  
RECEIVER  
MASTER  
TRANSMITTER/  
RECEIVER  
MASTER  
TRANSMITTER  
TRANSMITTER/  
RECEIVER  
RECEIVER  
3847 FHD F15  
8