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X24012S 参数 Datasheet PDF下载

X24012S图片预览
型号: X24012S
PDF下载: 下载PDF文件 查看货源
内容描述: 串行E2PROM [Serial E2PROM]
分类和应用: 可编程只读存储器
文件页数/大小: 14 页 / 271 K
品牌: ICMIC [ IC MICROSYSTEMS ]
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X24012  
Current Address Read  
Internally the X24012 contains an address counter that  
maintains the address of the last word accessed,  
Random Read  
Random read operations allow the master to access any  
memory location in a random manner. Prior to issuing  
incremented by one. Therefore, if the last access (either a  
read or write) was to address n, the next read operation  
the slave address with the R/W bit set to one, the master must  
first perform a “dummy” write operation. The master  
would access data from address n + 1. Upon receipt of the  
slave address with R/W set to one, the X24012  
issues the start condition, and the slave address followed  
by the word address it is to read. After the word  
issues an acknowledge and transmits the eight bit word  
during the next eight clock cycles. The read operation is  
address acknowledge, the master immediately reissues the  
start condition and the slave address with the R/W bit  
terminated by the master; by not responding with an  
acknowledge and by issuing a stop condition. Refer to  
set to one. This will be followed by an acknowledge from the  
X24012 and then by the eight bit word. The read  
Figure 7 for the sequence of address, acknowledge and data  
transfer.  
operation is terminated by the master; by not responding with  
an acknowledge and by issuing a stop condition.  
Refer to Figure 8 for the address, acknowledge and data  
transfer sequence.  
Figure 7. Current Address Read  
S
T
S
T
SLAVE  
A
BUS ACTIVITY:  
ADDRESS  
R
T
MASTER  
O
P
SDA LINE  
S
P
A
C
BUS ACTIVITY:  
X24012  
DATA  
K
3847 FHD F12  
Figure 8. Random Read  
S
T
A
R
T
S
T
A
R
T
S
T
SLAVE  
ADDRESS  
WORD  
ADDRESS n  
SLAVE  
ADDRESS  
BUS ACTIVITY:  
MASTER  
O
P
SDA LINE  
S
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:  
X24012  
DATA n  
3847 FHD F13  
7