iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 25/29
B iS S
0x 00
0x 0F
0x 10
0x 1F
0x 20
R AM
0x 00
0x 0F
E E P R O M
B ank 0
B ank 0
0x 00 C onfi gur ati on
n = 0
C onfi gur ati on
D ata
D ata
0x 0F
0x 10
0x 2F
- - -
R /W
- 16
unus ed
0x 30 not av ai l abl e
0x 31 E D S B ank
0x 41...0x 7F
0x 32
P r ofi l e ID
0x 33
0
x
3
F
0x 34
S er i al N umber
0x 40
0x 41
0x 42
0x 43
0x 44
0x 47
0x 48
0x 77
0x 78
0x 7D
0x 7E
0x 7F
Ba nk Sel e cti on ®n
0x 37
0x 38
R
R
/
W
S l av e R egi s ter
0x 6 7
0x 68
D ev i c e ID
0x 6D
0x 78
0x 7D
0x 7E
0x 7F
0x 6E
M
a
n
u
f
a
c
t
.
I
D
0x 6F
R O M
0x 70
not av ai l abl e
0x 7F
B
a
n
k
1
B ank 1...7
n
=
1
0
x
8
0
0x 00
0x 3F
0x B F
B ank 2
0x C 0
0x F F
R /W
R
n
=
2
B
a
n
k
3
n = 3
n = ...14
0
x
1
0
0
0
x
1
3
F
B ank 8...15
R /W R /W
.
.
.
0
x
3
F
F
B
a
n
k
.
.
.
1
4
B
a
n
k
1
5
n
=
1
5
0x 400
0x 43F
n
o
t
a
v
a
i
l
a
b
l
e
R
P
L
0
R
P
L
1
R
e
g
i
s
t
e
r
P
r
o
t
e
c
t
i
o
n
Figure 18: Registers and addressing
STARTUP BEHAVIOR
After the supply has been turned on (power on reset), So that it is always possible to configure the setup us-
iC-NQC reads the configuration data from the EEP- ing the I/O interface - even without an EEPROM - iC-
ROM and during this phase halts error pin NERR ac- NQC first ignores parameters TIMO, TOA and RPL.
tively on a low signal (open drain output) as well as
data output SLO on a high signal.
The I/O interface can then be addressed in BiSS C
protocol with the longest timeout (30 µs maximum),
After a successful CRC the data output is released without safety settings being observed (cf. RPL =
and the error indication at pin NERR reset; an exter- 0x0).This allows the configuration to be written to RAM
nal pull-up resistor can supply a high signal. iC-NQC addresses 0x01 to 0x0C and to address 0x00. Ad-
then switches to normal operation and determines the dress 0x00 must be written to last of all and triggers an
current angle position, providing that a sensor is con- internal reset (see description on page 20).
nected up to it and there is no amplitude error (or this
is deactivated).
A short timeout of 3 µs maximum can be temporar-
ily activated by writing value 0x07 to address 0x7C
Should the CRC prove unsuccessful due to a data er- (address 124d) to keep the device configuration time
ror (disrupted transmission, no EEPROM or the EEP- shorter.
ROM is not programmed), the configuration phase is
automatically repeated. After a third failed attempt, the When operated without an EEPROM, iC-NQC does
procedure is aborted and error pin NERR remains ac- not respond to higher addresses - with the exception
tive, displaying a permanent low.
of the BiSS addresses reserved for manufacturers and
device IDs (0x78 to 0x7F). This address area supplies
After startup, iC-NQC does not recognize a defined the chip version from the ROM.
configuration; the configuration RAM can contain any
values.
ICHAUS [ IC-HAUS GMBH ]
