iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 15/39
I2C Slave Mode (ENSL = 1)
Register
Read access via I2C slave mode (ENSL = 1)
In this mode iC-MQ behaves like an I2C slave with the
device ID 0x55 and the configuration interface permits
write and read accesses to iC-MQ’s internal registers.
RAM Addr Content
0x00-0x21 Configuration data
(see EEPROM addresses 0x00-0x21)
0x22-0x2A Not available
0x2B-0x2E Configuration data
For chip release verification purposes an identification
value is stored under ROM address 0x2F; a write ac-
cess to this address is not permitted.
(see EEPROM addresses 0x2B-0x2E)
Chip release CHPREL(7:0)
0x30-0x33 Configuration data
(see EEPROM addresses 0x30-0x33)
0x2F
CHPREL
Code
0x00
Adr 0x2F, bit 7:0 (ROM)
Chip Release
Not available
iC-MQ 3
0x34-0x3A Not available
0x3B-0x3E Configuration data
(see EEPROM addresses 0x2B-0x2E)
0x04
0x3F
Chip release CHPREL(7:0)
0x08
iC-MQ X
0x40-0x43 Current error memory (only active when enabled by
EMASKE; messages will be transferred to
0x09
iC-MQ X1
EEPROM Addresses 0x30-0x33)
0x44-0x7F Not available
Table 7: Chip Release
Table 9: RAM Read Access
END
Code
0
Adr 0x02, bit 7
Function
Register
RAM Addr Access and conditions
Write access via I2C slave mode (ENSL = 1)
Sin/D converter and line driver disabled
(RAM configuration data invalid)
0x00
0x01
Changes possible, no restrictions
1
Restart of Sin/D conversion, line driver active
(RAM configuration data valid)
Changes possible
(wrong entries for CFGIBN can limit functions)
0x02
Changes to bits 6:0 are permitted only when Sin/D
conversion is halted (END = 0, ie. bit 7);
Table 8: Configuration Enable
Restarting Sin/D conversion by changing END (bit
7) is permitted only with no changes of operating
mode (bits 6:0 remain as set)
0x03-0x16 Changes possible, no restrictions
0x17
Changes to bits 7:4 and 2:0 are permitted
(ENSL, bit 3 must be kept 1)
0x18
Changes possible, no restrictions
0x19-0x21 Changes possible when Sin/D conversion is halted
(END = 0)
0x2B-0x2E Changes possible, no restrictions
0x2F-0x3F No write access permitted
0x40-0x43 No write access permitted
0x44-0x7F Not available
Table 10: RAM Write Access
Notes: The converter function should be halted by
END = 0 for the deletion of errors saved in the EEP-
ROM (Dev-ID 0x50, Addresses 0x30-0x33). Other-
wise active errors could be transferred to the EEP-
ROM again (from addresses 0x40-0x43 if enabled by
EMASKE).
ICHAUS [ IC-HAUS GMBH ]
