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IC-MN 参数 Datasheet PDF下载

IC-MN图片预览
型号: IC-MN
PDF下载: 下载PDF文件 查看货源
内容描述: 25位游标编码器, 3 -CH 。采样13位仙/ D插值 [25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION]
分类和应用: 编码器
文件页数/大小: 59 页 / 1705 K
品牌: ICHAUS [ IC-HAUS GMBH ]
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iC-MN 25-BIT NONIUS ENCODER  
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION  
Rev D1, Page 23/59  
SIGNAL CONDITIONING for MASTER-, SEGMENT- and NONIUS-Channel (x= M,S,N)  
DCPOS  
Addr. 0x0A; bit 6  
Polarity Isensor  
Code  
VREFin()  
2.5 V  
0
1
Negative  
Positive  
1.5 V  
Table 12: Input current polarity  
RIN  
Addr. 0x0A; bit 2:1  
Code  
Resistance  
1.6 kΩ  
0
1
2
3
2.3 kΩ  
3.2 kΩ  
4.6 kΩ  
Table 13: Input resistance with I mode  
Voltage Signals  
If the voltage signals are too large the input signal can  
be quartered by an internal divider. The voltage divider  
is referenced to the VREFin reference source which is  
set by DCPOS. In order to use the input voltage range  
of the input amplifier to its full capacity DCPOS should  
be set to 1 in voltage divider mode.  
Figure 7: Schematic of Input Stage  
The input stages for sine and cosine are instrumen-  
tation amplifiers and can process current and voltage  
signals; selection is made for all three tracks using  
UIN. Signal conditioning should be performed in the  
order given in the following.  
TUIN  
Code  
0
Addr. 0x0A; bit 3  
Function  
Not active  
UIN  
Code  
0
Addr. 0x0A; bit 0  
Function  
1
Voltage divider active  
Table 14: Input voltage divider  
I Mode: current inputs  
V Mode: voltage inputs  
1
Table 11: Signal mode  
Additionally, using CVREF the user can select whether  
VREFin is the reference potential generated internally  
or a voltage provided externally.  
CVREF  
Code  
00  
Addr. 0x0B; bit 4:3  
Function  
Generated internally  
01  
Reserved  
10  
Internal VREFin() output to pin ACOS*  
External ref. voltage supplied to pin ACOS  
*) No load permitted, buffer required.  
11  
Figure 8: Direction of current flow  
Note  
Table 15: VREF Source Selection  
Current Signals  
For current signals internal reference VREFin is  
adapted to the input current polarity using DCPOS.  
The input resistance is set using RIN (1:0). When All other settings are to be carried out for each indi-  
selecting the input resistance the average potentials vidual track separately. A small x in the register name  
SVDC and CVDC should be between 125 mV and stands for (M)aster, (S)egment and (N)onius respec-  
250 mV to obtain a reasonable offset calibration range. tively.  
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