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IC-MLEVALML1D 参数 Datasheet PDF下载

IC-MLEVALML1D图片预览
型号: IC-MLEVALML1D
PDF下载: 下载PDF文件 查看货源
内容描述: 霍尔位置传感器/编码器 [HALL Position Sensor / Encoder]
分类和应用: 传感器编码器
文件页数/大小: 17 页 / 327 K
品牌: ICHAUS [ IC-HAUS GMBH ]
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iC-ML  
HALL Position Sensor / Encoder  
Rev A3, Page 15/17  
angle between 0° and 180° the device counts up to  
the operating point; if this angle is between 180° and  
360°, it first counts down. Starting when the device is  
switched on all edges are output until the absolute po-  
sition is reached. The setup has to wait until a certain  
time has elapsed; this is dependent on the selected  
resolution and is the settling time of the sensor until the  
error bit is deleted plus the time needed to count up or  
down to the absolute position. With a resolution of 8  
bits and an angle of 180°, for example, this period con-  
stitutes 100 µs sensor settling time plus 128 times 4 µs  
until the absolute position has been pinpointed. The  
absolute position is thus available after a maximum of  
612 µs has elapsed.  
NEN  
NERR  
A
B
Z
Time [us]  
Figure 18: Incremental signals after switching on  
the device, counting down  
By way of example Figure 18 illustrates how the incre-  
mental interface behaves when the device first counts  
down to the absolute position and the magnetic tape  
Always starting at zero position, the device begins then moves forwards, with the sensor following with the  
searching for the absolute position, locating it as relevant sequence. The Z signal is synchronous with  
quickly as possible. If this positon corresponds to an A and B at low.  
Incremental CLK modes  
Mode NEN CFG1 CFG2 CFG3  
Inkr. CLK  
Port A  
Port B  
Port C  
Port D Res. Comments  
CLK 8 low high low open  
CLK 6 low high high open  
DIR 8 low high low high  
DIR 6 low high high high  
NCLKUP  
NCLKUP  
NCLK  
NCLKDN  
NCLKDN  
DIR  
NCLR  
NCLR  
NCLR  
NCLR  
NERR  
NERR  
NERR  
NERR  
8
6
8
6
NCLK  
DIR  
CLK-INC mode  
mented; with a rising edge of clock signal NCLKDN  
In CLK-INC mode two different count signals are and a high at NCLKUP the counter status is decre-  
provided for the countup and countdown sequences. mented. Two 4-bit counters can be cascaded here to  
Depending on the direction of rotation either signal create a full 8-bit counter.  
NCLKUP (pin A) is pulsed when the device counts  
up or signal NCLKDN (pin B) when the device counts  
down. In each case the remaining signal is high. The  
zero angle is displayed by the NCLR index track which  
NCLUP  
can serve as an asynchronous reset for an external  
counter.  
NCLDN  
Figure 19 demonstrates how iC-ML behaves in CLK-  
INC mode, firstly when it counts up from the zero po-  
sition and then, following a change in the direction of  
movement, when it counts back down to zero position.  
NCLR  
This mode permits the operation of external binary  
counter modules (such as 74HC/HCT193, for exam-  
ple), with signal NCLR (pin C) being used to reset the  
Time [us]  
counter. With a rising edge of clock signal NCLKUP  
and a high at NCLKDN the counter status is incre-  
Figure 19: CLK-INC mode  
 
 
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