iC-LNG 16-BIT OPTO ENCODER
WITH SPI AND SERIAL / PARALLEL OUTPUTS
Rev A1, Page 17/25
SVALID
signals whether an error occurred during the last com-
munication with the SPI interface or not.
Code
Description
0
1
Sensor data invalid
Sensor data valid
The master transmits the opcode REGISTER sta-
tus/data. iC-LNG immediately passes the opcode on
to MISO. iC-LNG then transmits the STATUS byte and
a DATA byte. The DATA byte is not available in iC-LNG
and is thus not defined.
Table 13: SVALID
REQ
CS
SCLK
MOSI
MISO
CS
OP
SCLK
OP
SV 0-7 SV 8-15
...
OP
MOSI
OP
STATUS DATA
MISO
8 cycles
8 cycles
Figure 9: SDAD status
Figure 11: REGISTER status/data
If only one slave is connected, the relevant SVALID bit
is placed at bit position 7 in the SVALID byte.
Read REGISTER (cont.)
REQ
The master transmits the opcode Read REGISTER
(cont.). Start address ADR, from which point data is
to be read, is transmitted in the 2nd byte. The slave
immediately outputs the opcode and address and then
transmits DATA1. The internal address counter is in-
cremented after each data package.
CS
SCLK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OP
OP
MOSI
MISO
SV 0
8 cycles
SVALID vector
If an error occurs during register readout (cont.), i.e.
the address is invalid, the requested data was not
valid on data byte clocking, etc., the internal address
counter is incremented no further and the FAIL error
bit is set in the status byte (Table 14).
Figure 10: SDAD status (one slave)
REGISTER status/data
The status of the last REGISTER communication or
the last data transmission can be queried using the
REGISTER status/data command. The STATUS byte
contains the information summarized in Table 14.
CS
SCLK
STATUS
OP
OP
ADR
ADR
MOSI
MISO
Bit
Name
Description of the status
report
DATA1 DATA2
...
7
ERROR
Opcode invalid. Sensor
data was invalid on
readout
8 cycles
6..4
3
-
Reserved
DISMISS
FAIL
Address refused
Data request has failed
Figure 12: Read REGISTER (cont.)
2
1
BUSY
Slave is busy with a
request
Write to REGISTER (cont.)
0
VALID
DATA is valid
The master transmits the opcode Write to REGISTER
(cont.). Start address ADR, from which point succes-
sive data DATA1-DATAn is to be written, is transmitted
in the 2nd byte. The slave immediately outputs the
opcode, address, and data at MISO. The slave incre-
NB
Display logic: 1 = true, 0 = false
Table 14: SPI status information
All status bits are updated with each register access. ments its internal address counter after each DATAn
The ERROR bit is the exception to the rule; this bit data package.
ICHAUS [ IC-HAUS GMBH ]
