iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 4/35
PACKAGING INFORMATION
PIN CONFIGURATION
oBGA LNB2C
(7.6 mm x 7.1 mm x 1.6 mm)
PIN FUNCTIONS
No. Name Function
C1 DIR Code Inversion Input /
Parallel Output Bit 13
C2 TNS Test Input NSIN /
Parallel Output Bit 14
1
2
3
4 5
6
C3 TNC Test Input NCOS /
Parallel Output Bit 15
A
B
C
C4 TPS
Test Input PSIN /
Parallel Output Bit 1
C5 TPC Test Input PCOS /
Parallel Output Bit 0
C6 NCOS Analog Voltage Output NCOS
D1 DOUT Shift Register Data Output /
Parallel Output Bit 10
D
E
D2 DIN
Shift Register Data Input /
Parallel Output Bit 11
D3 NSL
Shift Register Load Input (low active) /
Parallel Output Bit 12
D4 INCB Incremental Output B /
Parallel Output Bit 3
D5 INCA Incremental Output A /
Parallel Output Bit 2
D6 ERR Error Message Output (high active)
PIN FUNCTIONS
No. Name Function
A1 SCK SPI Clock Input
A2 VDD + 3 V ... +5.5 V I/O Ports Supply Voltage
A3 GND I/O Ports Ground
A4 LED LED Highside Current Source
A5 VDDA + 4 V ... +5.5 V Supply Voltage
A6 GNDA Ground
E1 GB
E2 GA
E3 CLK
E4 XJD
Gray-code Output B (MSB-1) /
Parallel Output Bit 7
Gray-code Output A (MSB) /
Parallel Output Bit 8
Shift Register Clock Input /
Parallel Output Bit 9
Adjustment Signal /
B1 CS
SPI Chip Select Input
Parallel Output Bit 6
B2 MISO SPI Data Output
E5 POK Power Ok Indication/
Parallel Output Bit 5
E6 INCZ Incremental Output Z /
Parallel Output Bit 4
B3 MOSI SPI Data Input
B4 PCOS Analog Voltage Output PCOS
B5 NSIN Analog Voltage Output NSIN
B6 PSIN Analog Voltage Output PSIN
Wiring unused input pins can be recommended, especially for pins DIR, TPS, TNS, TPC, TNC (e.g. via 10 kΩ to
GNDA).
For dimensional specifications refer to the package datasheet iC-LNB oBGA LNB2C, available separately.
ICHAUS [ IC-HAUS GMBH ]
