iC-LFL1402
256x1 LINEAR IMAGE SENSOR
y
inar
relim
p
Rev A3, Page 6/8
DESCRIPTION OF FUNCTIONS
Normal operation
Following an internal power-on reset the integration
and hold capacitors are discharged and the sample
and hold circuit is set to sample mode. A high signal
at SI and a rising edge at CLK triggers a readout cycle
and with it a new integration cycle.
In this process the hold capacitors of pixels 1 to 255
are switched to hold mode immediately (SNH = 1),
254
CLK
255
256
1
2
3
with pixel 256 (SNH256 = 1) following suit one clock
pulse later. This special procedure allows all pixels to
be read out with just 256 clock pulses. The integration
capacitors are discharged by a one clock long reset
signal (NRCI = 0) which occurs between the 2
nd
and
3
rd
falling edge of the readout clock pulse (cf. Figure
4). After the 255 pixels have been read out these are
again set to sample mode (SNH = 0), likewise for pixel
256 one clock pulse later (SNH256 = 0).
4
...
255
256
1
2
SI
V(AO)
Pix254
Pix255
Pix256
Pix1
Pix2
Pix3
...
Pix255
Pix256
Pix1
SNH
SNH256
NRCI
Integration Time Pixel 1−255
Integration Time Pixel 256
Figure 4: Readout cycle and integration sequence
If prior to the 256
th
clock pulse a high signal occurs
at SI the present readout is halted and immediately
reinitiated with pixel 1. In this instance the hold ca-
254
CLK
255
256
1
2
3
4
pacitors retain their old value i.e. hold mode prevails
(SNH/SNH256 = 0).
5
1
2
3
4
...
256
1
2
SI
V(AO)
Pix254
Pix255
Pix256
Pix1
Pix2
Pix3
Pix4
Pix5
Pix1
Pix2
Pix3
Pix4
...
Pix256
Pix1
SNH
SNH256
NRCI
Figure 5: Restarting a readout cycle
With more than 256 clock pulses until the next SI sig-
nal, pixel 1 is output without entering hold mode; the
output voltage tracks the voltage of the pixel 1 integra-
tion capacitor.
ICHAUS [ IC-HAUS GMBH ]
