Preliminary
Datasheet
DD2.X
PowerPC 750CL Microprocessor
1. General Information
The IBM
®
PowerPC
®
750™CL RISC microprocessor is a 32-bit implementation of the IBM PowerPC family.
This document contains pertinent physical and electrical characteristics of the IBM PowerPC 750CL RISC
Microprocessor revision DD2.X single chip module (SCM). The PowerPC 750CL Microprocessor is also
referred to as the 750CL throughout this document.
1.1 Features
This section summarizes the features of the 750CL implementation of the PowerPC Architecture™. Major
features of the 750CL include the following:
• Branch processing unit
• Fetches four instructions per clock
• Processes one branch per cycle and can resolve two speculations
• Executes single speculative stream during fetch of another speculative stream
• Has a 512-entry branch history table (BHT) for dynamic prediction
• Dispatch unit
• Has full hardware detection of dependencies, which are resolved in the execution units
• Dispatches two instructions to six independent units (system, branch, load/store, fixed-point unit 1,
fixed-point unit 2, or floating-point)
• Has serialization control (predispatch, postdispatch, execution, serialization)
• Decode
• Register file access
• Forwarding control
• Partial instruction decode
• Load/store unit
• Has single-cycle load or store cache access (byte, halfword, word, doubleword)
• Has effective address generation
• Allows hits under misses (one outstanding miss)
• Has single-cycle misaligned access within a doubleword boundary
• Has alignment, zero padding, sign extend for integer register file
• Converts floating-point internal format (using alignment and normalization)
• Sequences for load/store multiples and string operations
• Has store gathering
• Has cache and translation lookaside buffer (TLB) instructions
• Supports big-endian and little-endian byte addressing
• Supports misaligned little-endian in hardware
Version
2.5
December 2, 2008
General Information
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