Datasheet
DD2.X
Preliminary
PowerPC 750CL Microprocessor
5.10 Operational and Design Considerations
5.10.1 Level Protection
A level protection feature is included in the 750CL. This feature prevents ambiguous floating reference volt-
ages by pulling the respective signal line to the last valid or nearest valid state.
For example, if the input/output voltage level is closer to OVDD, the circuit pulls the I/O level to OVDD. If the I/O
level is closer to GND, the I/O level is pulled low. This self-latching circuitry keeps the floating inputs defined
and avoids meta-stability. In Table 5-4, Input/Output Usage, on page 51, these signals are defined as
“keeper” in the “Level Protect” column. The keeper circuits are not intended to hold a net at a particular logic
level, or to strongly hold a net at the current logic level. Strong noise can cause the net to switch.
The level protect circuitry provides no additional leakage current to the signal I/O; however, some amount of
current must be applied to the keeper node to overcome the level protection latch. Any pullup or pulldown
resistors should be 1k Ω or less to overcome the keeper current.
This feature allows the system designer to limit the number of resistors in the design and optimize placement
and reduce costs.
Note: Having a keeper on the associated signal I/O does not replace a pullup or pulldown resistor that is
needed by a separate device located on the 60x bus. The designer must supply any termination requirements
for these separate devices, as defined in their specifications.
5.10.2 Configuring the Processor During Reset
Operating modes of the processor such as the data bus width, DRTRY mode, and so forth are selected when
the processor exits reset mode (that is, when HRESET is deasserted). Specifically, selected pins are
sampled when HRESET transitions to the de-asserted state and the sampled value determines the operating
mode. The mode select pins and their descriptions follow.
Table 5-7. Summary of Mode Select
Mode
750CL
Sample TLBISYNC to select
High = 64-bit mode
32-bit mode
Low = 32-bit mode
Selects DRTRY mode. Sample DRTRY to select.
0 at HRESET transition
1 at HRESET transition
No DRTRY mode
DRTRY mode
Data retry mode
DRTRY must be de-asserted once the processor is configured for no-drtry
mode. This can be accomplished by driving DRTRY with a copy of HRESET.
QACK in a logical high state at the transition of HRESET from asserted to
negated enables standard precharge mode, the recommended default. See
Section 5.10.3.1 for details.
Standard/extended precharge mode
Continuously ground L2_TSTCLK to select 1.8 V bus operation. Continuously
connect L2_TSTCLK to OVDD to select 1.15 V bus mode.
I/O bus voltage (OVDD
PLL divider mode
)
PLL divider mode is selected by sensing the data bus write-only (DBWO) pin
at the transition of HRESET from low to high. For normal operation, DBWO
must be held low ('0') at the HRESET transition whenever noninteger proces-
sor-to-bus frequency ratios are selected (that is, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, 8.5,
and 9.5). DBWO can be held either low or high (= OVDD) for integer ratios.
Version 2.5
System Design Information
Page 63 of 70
December 2, 2008
IBM [ IBM ]
