Datasheet
DD2.X
PowerPC 750CL Microprocessor
Preliminary
3.6.1 IEEE 1149.1 AC Timing Specifications
Table 3-9 provides the IEEE 1149.1 (JTAG) AC timing specifications. The five JTAG signals are: test data
input (TDI), test data output (TDO), test mode select (TMS), test clock (TCK), and test reset (TRST).
Table 3-9. JTAG AC Timing Specifications (Independent of SYSCLK)
See Table 3-2 on page 22 for operating conditions.
Number
Characteristic
Min.
0
Max.
25
—
—
2
Unit
MHz
ns
Notes
TCK frequency of operation
TCK cycle time
1
2
40
15
0
TCK clock pulse width measured at +0.55 V
TCK rise and fall times
ns
3
ns
4
4
Specification obsolete, intentionally omitted
TRST assert time
—
25
1
—
—
—
—
5
—
5
ns
1
2
6
Boundary-scan input data setup time
Boundary-scan input data hold time
TCK to output data valid
ns
7
3
ns
2
8
2
ns
3, 5
3, 4
9
TCK to output high impedance
TMS, TDI data setup time
2
5
ns
10
11
12
13
14
1
—
—
5
ns
TMS, TDI data hold time
1
ns
TCK to TDO data valid
1
ns
5
4
TCK to TDO high impedance
TCK to output data invalid (output hold)
2
5
ns
0
—
ns
Notes:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by characterization and not tested.
5. Minimum specification guaranteed by characterization and not tested.
Electrical and Thermal Characteristics
Page 34 of 70
Version 2.5
December 2, 2008
IBM [ IBM ]
