Datasheet
DD2.X
Preliminary
PowerPC 750CL Microprocessor
3.6 60x Bus Output AC Specifications
Table 3-8 provides the 60x bus output AC timing specifications for the 750CL as defined in Figure 3-7 on
page 33.
Table 3-8. 60x Bus Output AC Timing Specifications
See Table 3-2 on page 22 for operating conditions.1, 4, 5
Part Numbers
≤
Part Numbers
>
733 MHz
Figure 3-7
Timing
Reference
Characteristic
Unit
ps
Notes
733 MHz
Min.
200
Max.
Min.
200
Max.
SYSCLK to Output Driven
(Output Enable Time)
12
—
—
13
14
SYSCLK to Output Valid
—
2.6
–
—
2.6
–
ns
ps
SYSCLK to Output Invalid (Output Hold)
500
500
SYSCLK to Output High Impedance
15
(all signals except address retry [ARTRY], address
bus busy [ABB], and data bus busy [DBB])
—
2.8
—
2.8
ns
SYSCLK to ABB and DBB high impedance after pre-
charge
16
17
—
—
1.0
2.7
—
—
1.0
2.7
tSYSCLK
ps
2
3
SYSCLK to ARTRY high impedance
before precharge
(0.2 ×
tSYSCLK) +
0.2
(0.2 ×
tSYSCLK) +
0.2
18
SYSCLK to ARTRY precharge enable
—
—
ps
19
20
Maximum delay to ARTRY precharge
—
—
1.0
2.0
—
—
1.0
2.0
tSYSCLK
tSYSCLK
2, 3
2, 3
SYSCLK to ARTRY high impedance after precharge
Notes:
1. All output specifications are measured from the VM of the rising edge of SYSCLK to the midpoint of the output signal in question
using a test load as shown in Figure 3-6 on page 32. Both input and output timings are measured at the pin. Timings are deter-
mined by design. Timing values apply while OVDD = 1.5 V nominal and OVDD = 1.8 V nominal.
2. tSYSCLK is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied
by the period of SYSCLK to compute the actual time duration of the parameter in question.
3. Nominal precharge width for ARTRY is 1.0 tSYSCLK
.
4. Guaranteed by design and characterization, and not tested.
5. See Figure 3-6 on page 32 and Figure 3-7 on page 33 for output loading and timing definitions.
Version 2.5
Electrical and Thermal Characteristics
December 2, 2008
Page 31 of 70
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