Datasheet
DD2.X
PowerPC 750CL Microprocessor
Preliminary
Figure 3-1. SYSCLK Input Timing Diagram
1
2
3
4
4
VIH
VM
SYSCLK
VIL
VM-SYSCLK: VDD/2
3.4 Spread Spectrum Clock Generator
3.4.1 Design Considerations
When designing with the spread spectrum clock generator (SSCG), there are a number of design issues that
must be taken into account.
SSCG creates a controlled amount of long-term jitter. For a receiving PLL in the 750CL to operate in this envi-
ronment, it must be able to accurately track the SSCG clock jitter.
The accuracy to which the 750CL PLL can track the SSCG clock is referred to as tracking skew. When
performing system timing analysis, the tracking skew must be added or subtracted to the I/O timing specifica-
tions because the tracking skew appears as a static phase error between the internal PLL and the SSCG
clock.
To minimize the impact on I/O timings, the following SSCG configuration is recommended:
• Down spread mode, less than or equal to 1% of the maximum frequency
• A modulation frequency of 32 kHz or less
1
• Linear sweep modulation or “Hershey’s Kiss” (as in a Lexmark profile) modulation profile as shown in
Figure 3-2 on page 27
In this configuration, the tracking skew is less than 100 ps.
1. See patent 5,631,920.
Electrical and Thermal Characteristics
Page 26 of 70
Version 2.5
December 2, 2008
IBM [ IBM ]
