Datasheet
DD2.X
Preliminary
PowerPC 750CL Microprocessor
3.3 Clock Specifications
Table 3-6 provides the clock AC timing specifications as defined in Figure 3-1 on page 26.
Table 3-6. Clock AC Timing Specifications
See Table 3-2 on page 22 for recommended operating conditions.1, 3, 5
Figure 3-1
Timing
Reference
Value
Max.
Characteristic
Unit
Notes
Min.
400
50
Processor frequency
SYSCLK frequency
1000
240
100
—
MHz
MHz
μs
Internal PLL relock time
Internal PLL reset time
—
4
5
10
μs
Single-Ended SYSCLK Specifications
2, 3
4
SYSCLK slew rate, single-ended
1.0
25
—
—
—
—
2.5
75
V/ns
%
2
SYSCLK duty cycle measured at Vm-SYsClk, single-ended
Jitter, over any 10 consecutive cycles
160
240
380
640
ps
6
6
6
6
Jitter, over any 50 consecutive cycles
ps
Jitter, over any 100 consecutive cycles
Jitter, over any 1000 consecutive cycles
ps
ps
Differential SYSCLK and SYSCLK Specifications
2, 3
4
SYSCLK and SYSCLK slew rate, differential
SYSCLK and SYSCLK duty cycle measured at Vm-SYsClk, differential
Jitter, cycle-to-cycle
1.50
40
3.0
60
V/ns
%
7
8
—
200
2.5
ps (P - P)
%
Jitter, long term
—
Notes:
1. Caution: The SYSCLK frequency and the PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL frequency do not exceed their respective maximum or minimum operating frequencies.
Refer to the PLL_CFG[0:4] signal description in Table 5-1, 750CL Microprocessor PLL Configuration, on page 44 for valid
PLL_CFG[0:4] settings.
2. The slew rate for the single-ended SYSCLK inputs is measured from 0.4 to 0.75 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time
required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. Also note that hard reset
(HRESET) must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
5. Midpoint voltage (VM) for SYSCLK and SYSCLK is VDD/2. The SYSCLK and SYSCLK input voltage range depends on OVDD, but
V
M is a function of VDD.
6. This is the maximum deviation from nominal in the timing of the rising edge of SYSCLK over the indicated number of cycles.
7. The slew rate for SYSCLK and SYSCLK is measured between the 10% and 90% points of each clock input.
8. Long term jitter is given as a percentage of the input clock period occurring over a 10 μs interval.
Version 2.5
Electrical and Thermal Characteristics
Page 25 of 70
December 2, 2008
IBM [ IBM ]
