Datasheet
DD2.X
Preliminary
PowerPC 750CL Microprocessor
2. Overview
The IBM PowerPC 750CL RISC Microprocessor, also called the 750CL, is targeted for high-performance,
low-power systems using a 60x bus. The 750CL also includes an internal 256 KB L2 cache with an on-board
error correction code (ECC) algorithm.
2.1 Block Diagram
Table 2-1. PowerPC 750CL Microprocessor Block Diagram
Control Unit
Instruction Fetch
Branch Unit
Completion
32K Instruction Cache
BHT/
BTIC
System
Unit
Dispatch
GPRs
LSU
FPRs
FPU
FXU1
FXU2
Rename
Buffers
Rename
Buffers
256 KB
L2 Cache
L2 Tags
60x
32 KB Data Cache
BIU/DMA
BHT
BIU
Branch history table
Bus interface unit
BTIC
DMA
FPR
FPU
FXU
GPR
L2
Branch target instruction cache
Direct memory access
Floating-point register
Floating-point unit
Fixed-point unit
General purpose register
Level 2
LSU
Load/store unit
Version 2.5
December 2, 2008
Overview
Page 19 of 70
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