Datasheet
DD2.X
Preliminary
• 64-byte cache line organized as two 32-byte sectors
PowerPC 750CL Microprocessor
• L2 frequency at core speed
• Selectable 32-byte, 64-byte, or 128-byte L2 cache loads
• Error correction code (ECC) protection on cache array
• Bus interface
• Compatible with the 60x processor interface
• Has a 32-bit address bus
• Has a 64-bit data bus (also supports 32-bit data bus mode)
• Supports bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x,
8x, 8.5x, 9x, 9.5x, and 10x
• Bus transaction pipeline depth of 2, 3, or 4 transactions (selectable)
• Testability
• Level sensitive scan design (LSSD)
• JTAG interface
1.2 Processor Version Register
The 750CL has the following Processor Version Register (PVR) values for the respective design revision
levels.
Table 1-1. 750CL Processor Version Register (PVR)
750CL Design Revision Level
DD2.0
PVR
0x00087210
Version 2.5
December 2, 2008
General Information
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