IBMN625404GT3B
IBMN625804GT3B
256Mb Double Data Rate Synchronous DRAM
Preliminary
Revision Log
Rev
Contents of Modification
Changed to Preliminary classification.
Removed all references to stacks.
Changed nomenclature for “PC”200 to “DDR”200.
Updated ordering information.
Clarified DM definition during a write.
Updated power sequencing requirements for DRAM initialization.
Updated CK and CK input capacitance. Added V-I matching ratio.
Changed “Weak” to “Half” to match JEDEC terminology.
Removed Note from Half-Strength driver notes indicating SSTC compatibility.
Inserted DQS/DQ/DM Slew Rate table.
10/18/00
Updated I
Added I
current term as defined at JEDEC.
DD7
DD5.
Moved all notes to a table behind the AC parameters.
Updated t max to 12ns for all speed sorts.
CK
Updated CL=2 support for the 75N device to be t
=10ns
CKmin
Added notes 18 and 19 to t and t to describe derating curves for these parameters.
DS
DH
Added note 17 to t and t to describe derating curves for these parameters.
IH
IS
Updated Note 14 to indicate tester characterization.
Redefined t specification, added note 16 to clarify.
DAL
Removed repetitive info from the AC timing table expressed in clock cycles.
Removed all references to half strength drivers.
Updated the extended mode register definition to indicate A =1 is reserved.
1
1/01
Removed V (DC) to be consistent with the industry standard DDR specification.
IX
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Use is further subject to the provisions at the end of this document.
29L0011.E36997B
1/01
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