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IBMN625405GT3B-8N 参数 Datasheet PDF下载

IBMN625405GT3B-8N图片预览
型号: IBMN625405GT3B-8N
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 64MX4, 0.8ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 79 页 / 1328 K
品牌: IBM [ IBM ]
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IBMN625404GT3B  
IBMN625804GT3B  
Preliminary  
256Mb Double Data Rate Synchronous DRAM  
Revision Log  
Rev  
Contents of Modification  
10/99  
Initial release; Rev 0.1.  
1st Revision; Rev 0.2.  
Corrected p/n labelling for stacked devices. Changed 4B to 4K to signify stacked devices have 2 CKE pins, not 1  
CKE pin.  
Correct typo in Features section. Avg period refresh interval is 7.8µs not 7.8ns.  
Added note to pinout that QFC\ is an optional feature and must be specified upon purchasing.  
Modified AC and DC operating conditions for V , I , I , V . Added Iolw and Iohw DC parameters.  
ix ol oh  
ref  
Added DDR device labeling guild to device ordering information.  
Added p/n’s for devices that support the QFC\ option.  
Clarified description of Extended mode register, DLL Enable/Disable, Output drive strength, and QFC\ Enable  
/Disable.  
Added note to Pinout diagrams that QFC\ is an optional feature and must be specified via p/n when ordering  
devices.  
Removed the word “optional” from the Drive Strength Field in the Extended Mode Register Definition Diagram.  
Changed Vil (DC) and V (DC) to V -0.15V and V +0.15V, respectively.  
ih  
ref  
ref  
Changed Vil (AC) and V (AC) to V -0.31V and V +0.31V, respectively.  
ih  
ref  
ref  
Added Idd values for PC200 and PC266 speed sorts.  
Removed t (min) and t (min) from AC timing parameters.  
DQSQ  
DQSQA  
03/24/00  
Changed AC Timing Load Circuit diagram and added QFC\ Timing Load Circuit diagram.  
Added t parameter to AC timings and modified t & t to reflect slow and fast input slew rates.  
IPW  
IS  
IH  
Changed Input capacitance for all inputs and outputs (except CK and CK\).  
Added delta input capacitance specification for all inputs and outputs (except QFC\)  
AC Operating Characteristics: changed definition of Vix from input “closing” point to input “crossing” point.  
Added new AC timing parameter (t ).  
HP  
Replaced AC timing parameter t with t  
DV  
QH  
Modified Dataout Read Timing Diagram to remove reference to t and replace with t and t .  
QH  
DV  
Changed RAS, CAS, and WE to RAS, CAS, and WE where applicable.  
Added further clarification to “Initialization” description.  
HP  
Added tRAS lockout description under auto precharge description with supporting timing diagram.  
Added t  
Added t  
as a new parameter to AC timing parameters.  
lock out support to Features section.  
RAP  
RAS  
Removed statement from Auto Refresh section that states “a maximum of 8 auto refresh commands can be  
posted in the system”.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
29L0011.E36997B  
1/01  
Page 77 of 79  
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