IBMN625404GT3B
IBMN625804GT3B
256Mb Double Data Rate Synchronous DRAM
Preliminary
Data Input (Write) (Timing Burst Length = 4)
tDSL
tDSH
DQS
tDH
tDS
DI n
DQ
tDH
tDS
DM
DI n = Data In for column n.
3 subsequent elements of data in are applied in programmed order following DI n.
Don’t Care
Data Output (Read) (Timing Burst Length = 4)
CK
CK
tHP
tHP
tHP
tHP1
tHP2
tHP3
tHP4
DQS
tQH2
tQH4
tDQSQ
tQH1
tDQSQ
tQH3
DQ
tDQSQ
tDQSQ
t
is the half cycle pulse width for each half cycle clock. t is referenced to the clock duty cycle only
HP
HP
and not to the data strobe (DQS) duty cycle.
Data Output hold time from Data Strobe is shown as t . t is a function of the clock high or low time (t
)
HP
QH QH
for that given clock cycle. Note correlation of t to t in the diagram above (t
to t
, etc.).
QH1
HP
QH
HP1
t
(max)occurs when DQS is the earliest among DQS and DQ signals to transition.
DQSQ
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Use is further subject to the provisions at the end of this document.
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