IBMN612404GT3B
IBMN612804GT3B
Preliminary
128Mb Double Data Rate Synchronous DRAM
Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute
Specifications
(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)
DDR266A (7N)
DDR266B (75N)
DDR200 (8N)
Symbol
Parameter
Unit
Notes
Min
− 0.75
− 0.75
0.45
0.45
7
Max
+ 0.75
+ 0.75
0.55
0.55
12
Min
− 0.75
− 0.75
0.45
Max
+ 0.75
+ 0.75
0.55
Min
− 0.8
− 0.8
0.45
0.45
8
Max
+ 0.8
+ 0.8
0.55
0.55
12
t
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
ns 1, 2, 3, 4
ns 1, 2, 3, 4
AC
t
DQSCK
t
t
t
1, 2, 3, 4
1, 2, 3, 4
CH
CK
CK
t
CK low-level width
0.45
0.55
CL
CK
t
CL = 2.5
7.5
12
ns 1, 2, 3, 4
Clock cycle time
CL = 2.0
7.5
12
t
10
12
10
12
ns 1, 2, 3, 4
CK
DH
10
12
1, 2, 3,
ns
t
DQ and DM input hold time
0.5
0.5
0.6
4, 18, 19
1, 2, 3,
ns
t
DQ and DM input setup time
0.5
0.5
1.75
0.6
2
DS
4, 18, 19
t
DQ and DM input pulse width (each input)
1.75
ns 1, 2, 3, 4
DIPW
1, 2, 3,
4, 5
t
Data-out high-impedance time from CK/CK − 0.75
+ 0.75
+ 0.75
− 0.75
+ 0.75
+ 0.75
− 0.8
+ 0.8
+ 0.8
ns
HZ
1, 2, 3,
4, 5
t
Data-out low-impedance time from CK/CK
− 0.75
− 0.75
− 0.8
ns
LZ
DQS-DQ skew (DQS & associated DQ sig-
nals)
t
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.6
+ 0.6
ns 1, 2, 3, 4
ns 1, 2, 3, 4
DQSQ
t
DQS-DQ skew (DQS & all DQ signals)
minimum half clk period for any given
DQSQA
t
t
t
CH
CH
CH
t
cycle; defined by clk high (t ) or clk low
or
or
or
t
1, 2, 3, 4
HP
CH
CK
(t ) time
t
t
t
CL
CL
CL
CL
t
-
t
-
t
-
HP
HP
HP
t
Data output hold time from DQS
t
t
t
t
t
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
QH
CK
CK
CK
CK
CK
0.75ns
0.75ns
1.0ns
Write command to 1st DQS latching transi-
tion
t
0.75
1.25
0.75
1.25
0.75
1.25
DQSS
DQS input low (high) pulse width (write
cycle)
t
0.35
0.2
0.35
0.2
0.35
0.2
DQSL,H
DQS falling edge to CK setup time (write
cycle)
t
DSS
DQS falling edge hold time from CK (write
cycle)
t
0.2
14
0
0.2
15
0
0.2
16
0
DSH
t
Mode register set command cycle time
Write preamble setup time
ns 1, 2, 3, 4
MRD
1, 2, 3,
4, 7
t
ns
WPRES
1, 2, 3,
4, 6
t
Write postamble
Write preamble
0.40
0.25
0.60
0.40
0.25
0.60
0.40
0.25
0.60
t
WPST
CK
t
t
1, 2, 3, 4
WPRE
CK
2, 3, 4,
11, 13,
14
Address and control input hold time (fast
slew rate)
t
0.9
0.9
1.1
ns
IH
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Use is further subject to the provisions at the end of this document.
06K0566.F39350B
1/01
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