.
IBMN325164CT3 IBMN325804CT3
IBMN325404CT3
Preliminary
256Mb Synchronous DRAM - Die Revision B
Pin Description
CK
CKE (CKE0, CKE1)
CS (CS0, CS1)
RAS
Clock Input
Clock Enable
DQ0-DQ15
Data Input/Output
Data Mask
DQM, LDQM, UDQM
Chip Select
V
Power (+3.3V)
Ground
DD
Row Address Strobe
Column Address Strobe
Write Enable
V
SS
CAS
V
Power for DQs (+3.3V)
Ground for DQs
No Connection
—
DDQ
WE
V
SSQ
BA1, BA0
A0 - A12
Bank Select
NC
—
Address Inputs
Input/Output Functional Description
Symbol
Type
Polarity
Function
Positive
Edge
CK
Input
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
CKE, CKE0,
CKE1
Active
High
Activates the CK signal when high and deactivates the CK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
Input
CS (CS0, CS1 for stacked devices) enables the command decoder when low and disables the
CS, CS0, CS1
Input Active Low command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation
to be executed by the SDRAM.
RAS, CAS, WE Input Active Low
BA1, BA0
A0 - A12
Input
—
Selects which bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 and A11 defines the column address (CA0-CA9,
CA11), when sampled at the rising clock edge. Assume the x4 organization.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10
is high, auto-precharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is
low, autoprecharge is disabled.
Input
—
During a Precharge command cycle, A10 is used in conjunction with BA0, BA1 to control which
bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If
A10 is low, then BA0 and BA1 are used to define which bank to precharge.
Input-
Output
DQ0 - DQ15
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled
high. In x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers,
respectively. In Read mode, DQM has a latency of two clock cycles and controls the output buff-
ers like an output enable. DQM low turns the output buffers on and DQM high turns them off. In
Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to
be written if it is low but blocks the write operation if DQM is high.
DQM
LDQM
UDQM
Active
High
Input
V
, V
Supply
Supply
—
—
Power and ground for the input buffers and the core logic.
DD
SS
V
V
Isolated power supply and ground for the output buffers to provide improved noise immunity.
DDQ SSQ
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K0608.F39375A
10/00
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