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IBMN312804CT3B-75H 参数 Datasheet PDF下载

IBMN312804CT3B-75H图片预览
型号: IBMN312804CT3B-75H
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 16MX8, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 66 页 / 2855 K
品牌: IBM [ IBM ]
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Preliminary
IBMN312804CT3
IBMN312404CT3
128Mb Synchronous DRAM - Die Revision B
IBMN312164CT3
Bank Activate Command
In relation to the operation of a fast page mode DRAM, the Bank Activate command correlates to a falling
RAS signal. The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the
rising edge of the clock. The Bank Select address BS0 - BS1 is used to select the desired bank. The row
address A0 - A11 is used to determine which row to activate in the selected bank. Activation of banks within
both decks of a 2-High stacked device is allowed.
The Bank Activate command must be applied before any Read or Write operation can be executed. The
delay from when the Bank Activate command is applied to when the first read or write operation can begin
must meet or exceed the RAS to CAS delay time (t
RCD
). Once a bank has been activated it must be pre-
charged before another Bank Activate command can be applied to the same bank. The minimum time interval
between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the
device (t
RC
). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B
and vice versa) is the Bank to Bank delay time (t
RRD
). The maximum time that each bank can be held active
is specified as t
RAS(max)
.
Bank Activate Command Cycle
(CAS Latency = 3, t
RCD
= 3)
T0
CK
..........
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
ADDRESS
Bank A
Row Addr.
RAS-CAS delay (
t
RCD
)
Bank A
Activate
Bank A
Col. Addr.
..........
Bank B
Row Addr.
Bank A
Row Addr.
RAS - RAS delay time (
t
RRD
)
Write A
with Auto
Precharge
Bank B
Activate
Bank A
Activate
COMMAND
: “ or “
H”
L”
NOP
NOP
..........
NOP
NOP
RAS Cycle time (
t
RC
)
Bank Select
The Bank Select inputs, BS0 and BS1, determine the bank to be used during a Bank Activate, Precharge,
Read, or Write operation.
Bank Selection Bits
BS0
0
1
0
1
BS1
0
0
1
1
Bank
Bank 0
Bank 1
Bank 2
Bank 3
06K7582.H03335A
01/01
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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