IBMN312164CT3
IBMN312404CT3
IBMN312804CT3
128Mb Synchronous DRAM - Die Revision B
Preliminary
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a
high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first
or second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that
point the Write Command will have control of the DQ bus.
Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
DQM high for CAS latency = 2 only.
Required to mask first bit of READ data.
DQM
NOP
READ A
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DIN A
DIN A
DIN A
DIN A
DIN A
DIN A
0
0
1
2
3
3
tCK2, DQs
CAS latency = 3
DIN A
DIN A
2
1
tCK3, DQs
: “H” or “L”
©IBM Corporation. All rights reserved.
06K7582.H03335A
01/01
Use is further subject to the provisions at the end of this document.
Page 12 of 66
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