IBMB3N64644HCB
IBMB3N64734HCB
Preliminary
64M x 64/72 Two-Bank Unbuffered SDRAM Module
AC Characteristics (TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
1. An initial pause of 200µs, with DQMB0-7 and CKE0-CKE1 held high, is required after power-up. A Pre-
charge All Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles
before or after the Mode Register Set operation.
2. The Transition time is measured between V and V (or between V and V ).
IH
IL
IL
IH
3. In addition to meeting the transition rate specification, the clock and CKE must transit between V and
IH
V (or between V and V ) in a monotonic manner.
IL
IL
IH
4. AC timing tests have V = 0.8 V and V = 2.0 V with the timing referenced to the 1.40V crossover point
IL
IH
5. AC measurements assume t =1.2 ns.
T
AC Characteristics Diagrams
tT
tCKH
VIH
1.4V
VIL
Clock
tCKL
tSETUP
tHOLD
Output
Zo = 50Ω
50pF
Input
1.4V
AC Output Load Circuit
tOH
tAC
tLZ
Output
1.4V
06K3767.H01636
11/00
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Use is further subject to the provisions at the end of this document.
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