IBMB3N64644HCB
IBMB3N64734HCB
64M x 64/72 Two-Bank Unbuffered SDRAM Module
Preliminary
Operating, Standby, and Refresh Currents (TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
Organization
Parameter
Symbol
Test Condition
Units Notes
-x64
x72
Operating Current
= t (min), t = min
Active-Precharge command cycling
without Burst operation
1 bank operation
t = t (min), t = min
RC
Active-Precharge command
cycling without Burst operation
t
RC
RC
CK
RC
CK
I
1440
1620
mA
1, 3, 4
CC1
CKE0, CKE1 ≤ V (max), t
=
IL
CK
CK
CK
CK
CK
I
min,
32
32
36
36
mA
mA
mA
mA
mA
2
CC2P
S0 - S3 =V (min)
IH
Precharge Standby Current in Power
Down Mode
CKE0, CKE1 ≤ V (max), t
Infinity,
S0 - S3 =V (min)
=
IL
I
2
CC2PS
IH
CKE0, CKE1 ≥ V (min), t
min,
S0 - S3 =V (min)
=
IH
I
480
128
960
540
144
1080
2, 5
2, 6
2, 5
CC2N
IH
Precharge Standby Current in Non-
Power Down Mode
CKE0, CKE1 ≥ V (min), t
Infinity,
S0 - S3 =V (min)
=
=
IH
I
CC2NS
IH
CKE0, CKE1 ≥ V (min), t
IH
I
min,
CC3N
S0 - S3 =V (min)
IH
No Operating Current
(Active state: 4 bank)
CKE0, CKE1 ≤ V (max), t
=
IL
CK
min,
I
96
108
mA
2, 7
CC3P
S0 - S3 =V (min)
IH
(Power Down Mode)
t
= min,
CK
Read/ Write command cycling,
multiple banks active,
gapless data, BL = 4
Burst Operating Current
I
1440
1880
1620
2115
mA
mA
1, 4, 8
1
CC4
t
= min,
CK
Auto (CBR) Refresh Current
I
I
CC5
CC6
CBR command cycling
Self Refresh Current
CKE0, CKE1 ≤ 0.2V
48
30
54
30
mA
2
9
Serial PD Device Standby Current
I
V
= GND or V
DD
µA
SB
IN
Serial PD Device Active Power Sup-
ply Current
I
SCL Clock Frequency = 100KHz
1
1
mA
10
CCA
1. The specified values are for one DIMM bank in the specified mode, and the other DIMM bank in Active Standby (I
2. The specified values are for both DIMM banks operating in the specified mode.
).
CC3N
3. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t and t
.
RC
CK
Input signals are changed up to three times during t (min).
RC
4. The specified values are obtained with the output open.
5. Input signals are changed once during three clock cycles.
6. Input signals are stable.
7. Active Standby current will be higher if clock suspend is entered during a Burst Read cycle (add 1mA per DQ).
8. Input signals are changed once during t
.
CK(min)
9. V = 3.3V.
DD
10. As follows:
•
Input pulse levels V x 0.1 to V x 0.9
DD DD
•
•
Input rise and fall times 10ns
Input and output timing levels V x 0.5
DD
•
Output load 1 TTL gate and CL=100pf
06K3767.H01636
11/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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