IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
For ingress data packets, header bytes H1 and H2 contain the packet destination bitmap, which designates
the output ports to which the packet is destined and, thereby, the output queues into which the packet will be
enqueued (see Tables 3-6 and 3-7). For the PowerPRS Q-64G, the destination bitmap is a logical bitmap.
Each logical port can be mapped to any physical port of the same subswitch using the Bitmap Mapping
Register (page 128). For example, logical bitmap 0 can address physical port 1 (rather than physical port 0).
When a destination bitmap bit is set to ‘1’, the packet is routed to the corresponding logical port. The bitmap
field can point to multiple output ports. If the destination bitmap value is all zeros, the packet is recognized as
a control packet.
Table 3-6. Ingress Data Packet and Control Packet, Byte H1 in the 256-Gbps Configuration
Packet Destination
Byte
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
H1
(high or low channel)
for extended bitmap
(byte H0) = 0
Output
port 0
Output
port 1
Output
port 2
Output
port 3
Output
port 4
Output
port 5
Output
port 6
Output
port 7
H1
(high or low channel)
for extended bitmap
(byte H0) = 1
Output
port 8
Output
port 9
Output
port 10
Output
port 11
Output
port 12
Output
port 13
Output
port 14
Output
port 15
In the 256-Gbps configuration, four PowerPRS Q-64Gs are configured for internal speed expansion, in which
the device ports are paired as follows: physical port 0 is paired with physical port 1 to form logical port 0,
physical port 2 is paired with physical port 3 to form logical port 1, and so forth. For packet routing, if bit n of
the packet destination bitmap is set to ‘1’, the packet is routed to physical output ports (n × 2) and
[(n × 2) + 1]. For example, if bit 3 of the destination bitmap is set to ‘1’, the packet is routed to physical output
ports 6 and 7.
Table 3-7. Ingress Data Packet and Control Packet, Bytes H1 and H2 in the 512-Gbps Configuration
Packet Destination
Byte
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
H1
(high or low channel)
for extended bitmap
(byte H0) = 0
Output
port 0
Output
port 1
Output
port 2
Output
port 3
Output
port 4
Output
port 5
Output
port 6
Output
port 7
H2
(high or low channel)
for extended bitmap
(byte H0) = 0
Output
port 8
Output
port 9
Output
port 10
Output
port 11
Output
port 12
Output
port 13
Output
port 14
Output
port 15
H1
(high or low channel)
for extended bitmap
(byte H0) = 1
Output
port 16
Output
port 17
Output
port 18
Output
port 19
Output
port 20
Output
port 21
Output
port 22
Output
port 23
H2
(high or low channel)
for extended bitmap
(byte H0) = 1
Output
port 24
Output
port 25
Output
port 26
Output
port 27
Output
port 28
Output
port 29
Output
port 30
Output
port 31
3.3.5 Ingress Service Packet Format
The ingress service packet format for the PowerPRS Q-64G 16-Gbps configuration is presented in Figure
3-7. The packet qualifier byte (H0) is described in Tables 3-8 and 3-9.
prsq-64g.01.fm
December 20, 2001
Functional Description
Page 35 of 199
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