Datasheet
PowerPC 970FX RISC Microprocessor
List of Tables
Table 1-1. PowerPC 970FX Ordering and PVR for the Standard Lead Package Version ........................... 16
Table 1-2. PowerPC 970FX Ordering and PVR for the Reduced-Lead Package Version ........................... 17
Table 2-1. General Parameters of the PowerPC 970FX .............................................................................. 19
Table 3-1. Absolute Maximum Ratings ......................................................................................................... 21
Table 3-2. Recommended Operating Conditions ......................................................................................... 21
Table 3-3. Package Thermal Characteristics ............................................................................................... 22
Table 3-4. dc Electrical Specifications .......................................................................................................... 23
Table 3-5. Power Consumption for Standard-Lead Packages ..................................................................... 24
Table 3-6. Power Consumption for Reduced-Lead Packages ..................................................................... 25
Table 3-7. Power Consumption Throttle Back F/2 ........................................................................................ 26
Table 3-8. Clock ac Timing Specifications .................................................................................................... 26
Table 3-9. Processor-Clock Timing Relationship Between PSYNC and SYSCLK ....................................... 28
Table 3-10. Processor Interconnect SSB Driver Specifications ................................................................... 31
Table 3-11. Processor Interconnect SSB Printed Circuit Board Trace Specifications .................................. 31
Table 3-12. Processor Interconnect SSB Receiver Specifications ............................................................... 32
Table 3-13. Processor Interconnect SSB Timing Parameters for the Deskew and Clock Alignment ........... 32
Table 3-14. Eye-Size Requirements ............................................................................................................. 33
Table 3-15. Input ac Timing Specifications ................................................................................................... 34
Table 3-16. Input ac Timing Specifications for TBEN ................................................................................... 34
Table 3-17. Input ac Timing Specifications for HRESET .............................................................................. 34
Table 3-18. Asynchronous Type Output Signals .......................................................................................... 36
Table 3-19. Asynchronous Open Drain Output Signals ................................................................................ 36
Table 3-20. Asynchronous Open-Drain Bidirectional Signals ....................................................................... 36
Table 3-21. Input ac Timing Specifications ................................................................................................... 37
Table 3-22. Mode Select Type Input Signals ................................................................................................ 39
Table 3-23. Debug Pins ................................................................................................................................ 39
Table 3-24. JTAG ac Timing Specifications (Dependent on SYSCLK) ........................................................ 42
Table 4-1. Standard-Lead and Reduced-Lead Package, Layout, and Assembly Differences ..................... 49
Table 4-2. Pinout Listing for the CBGA Package ......................................................................................... 55
Table 4-3. Voltage and Ground Assignments ............................................................................................... 60
Table 5-1. PowerPC 970FX RISC Microprocessor Bus Configuration ......................................................... 63
Table 5-2. PowerPC 970FX RISC Microprocessor PLL Configuration ......................................................... 64
Table 5-3. System Configuration - Typical Examples of Pin Settings .......................................................... 65
Table 5-4. Recommended Decoupling Capacitor Specifications ................................................................. 67
Table 5-5. Recommended Minimum Number of Decoupling Capacitors ..................................................... 67
Table 5-6. PowerPC 970FX Debug and Bringup Pin Settings and Information ........................................... 69
Table 5-7. PowerPC 970FX Pins for Manufacturing Test Only .................................................................... 70
Table 5-8. Input/Output Signal Descriptions ................................................................................................. 71
Version 2.5
List of Tables
Page 7 of 78
March 26, 2007
IBM [ IBM ]
