Datasheet
PowerPC 970FX RISC Microprocessor
4. Dimensions and Physical Signal Assignments ...................................................... 45
4.1 Electrostatic Discharge Considerations ..................................................................................... 45
4.2 Mechanical Packaging .................................................................................................................. 45
4.2.1 Standard Lead Package Version ........................................................................................... 45
4.2.2 Reduced-Lead Package Version ........................................................................................... 48
4.2.2.1 Mechanical Specifications .............................................................................................. 49
4.2.2.2 Assembly Considerations ............................................................................................... 49
4.3 PowerPC 970FX Microprocessor Pinout Listings ...................................................................... 55
5. System Design Information ...................................................................................... 63
5.1 External Resistors ......................................................................................................................... 63
5.2 Phase-Locked Loop Configuration .............................................................................................. 63
5.2.1 Determining PLLMULT and BUS_CFG Settings ................................................................... 63
5.2.2 PLL_RANGE Configuration ................................................................................................... 64
5.2.3 Typical PLL and SYSCLK Configurations .............................................................................. 64
5.3 PLL Power Supply Filtering .......................................................................................................... 66
5.4 Decoupling Recommendations .................................................................................................... 67
5.4.1 Using the KVPRBVDD and KVPRBGND Pins ....................................................................... 67
5.5 Decoupling Layout Guide ............................................................................................................. 68
5.6 Pullup and Pulldown Recommendations .................................................................................... 69
5.7 Input-Output Use ........................................................................................................................... 71
5.7.1 Chip Signal I/O and Test Pins ................................................................................................ 71
5.8 Thermal Management Information ............................................................................................... 75
5.8.1 Thermal Management Pins .................................................................................................... 75
5.8.2 Reading Thermal Diode Calibration Data through JTAG ....................................................... 75
5.8.3 Heatsink Attachment and Mounting Forces ........................................................................... 76
5.9 Operational and Design Considerations ..................................................................................... 78
5.9.1 Power-On Reset Considerations ........................................................................................... 78
5.9.2 Debugging PowerPC 970FX Power-On and Reset Sequence .............................................. 78
5.9.3 I2C Addressing of PowerPC 970FX ....................................................................................... 78
Contents
Version 2.5
March 26, 2007
Page 4 of 78
IBM [ IBM ]
