Data Sheet
Preliminary
PowerPC 970FX
Figure 1-1. PowerPC 970FX Block Diagram ................................................................................................ 13
Figure 1-2. Part Number Legend .................................................................................................................. 16
Figure 3-1. Clock Differential HSTL Signal ................................................................................................... 24
Figure 3-2. Processor-Clock Timing Relationship Between PSYNC and SYSCLK ...................................... 25
Figure 3-3. Block Diagram of an SSB for a Processor Interconnect Implementation ................................... 26
Figure 3-4. Typical Implementation for a Single-ended Line ........................................................................ 27
Figure 3-5. Differential Clock Termination Circuitry ...................................................................................... 28
Figure 3-6. Post-IAP Eye Opening ............................................................................................................... 29
Figure 3-7. Asynchronous Input Timing ........................................................................................................ 31
Figure 3-8. HRESET and BYPASS Timing Diagram .................................................................................... 34
Figure 3-9. Spread Spectrum Clock Generator (SSCG) Modulation Profile ................................................. 36
Figure 3-10. JTAG Clock Input Timing Diagram ........................................................................................... 38
Figure 3-11. Test Access Port Timing Diagram ............................................................................................ 39
Figure 4-1. PowerPC 970FX Microprocessor for Mechanical Package, Leaded, for DD3.0x Parts (top and side)
41
Figure 4-2. PowerPC 970FX Microprocessor Mechanical Package, Leaded, for DD3.1x Parts (top and side)
42
Figure 4-3. PowerPC 970FX Microprocessor Bottom Surface Nomenclature of Mechanical Package, Leaded,
CBGA Package ............................................................................................................................................ 43
Figure 4-4. PowerPC 970FX Microprocessor for Mechanical Package, Reduced-Lead, for DD3.0x Parts (top
and side) ....................................................................................................................................................... 45
Figure 4-5. PowerPC 970FX Microprocessor Mechanical Package, Reduced-Lead, for DD3.1 Parts (top and
side) .............................................................................................................................................................. 46
Figure 4-6. PowerPC 970FX Microprocessor Bottom Surface Nomenclature of Reduced-Lead CBGA Package
47
Figure 4-7. PowerPC 970FX Ball Placement (Top View) ............................................................................. 48
Figure 4-8. PowerPC 970FX Ball Placement (Bottom View) ........................................................................ 49
Figure 5-1. PLL Power Supply Filter Circuit ................................................................................................. 60
Figure 5-2. Decoupling Capacitor (Decap) Locations ................................................................................... 62
Figure 5-3. PowerPC 970FX Thermal Diode Implementation ...................................................................... 70
Figure 5-4. Force Diagram for the PowerPC 970FX Package ..................................................................... 71
October 14, 2005
Page 5 of 74
IBM [ IBM ]
