Data Sheet
PowerPC 970FX
Preliminary
• Dynamic instruction cracking for some instructions allows for simpler inner core dataflow
- Dedicated dataflow for cracking one instruction into two internal operations
- Microcoded templates for longer emulation sequences
• Speculative superscalar inner core organization
• Aggressive branch prediction
- Prediction for up to two branches per cycle
- Support for up to 16 predicted branches in flight
- Prediction support for branch direction and branch addresses
• Out of order issue of up to ten operations into 10 execution pipelines
- Two load or store operations
- Two fixed-point register-register operations
- Two floating-point operations
- One branch operation
- One condition register operation
- One VMX permute operation
- One VMX ALU operation
• In order dispatch of up to five operations into distributed issue queue structure
• Register renaming on GPRs, FPRs, VRFs, CR Fields, XER (parts), FPSCR, VSCR, VRSAVE, Link
and Count
• Large number of instructions in flight (theoretical maximum of 215 instructions)
- Up to 16 instructions in instruction fetch unit (fetch buffer and overflow buffer)
- Up to 32 instructions in instruction fetch buffer in instruction decode unit
- Up to 35 instructions in 3 decode pipe stages and 4 dispatch buffers
- Up to 100 instructions in the inner-core (after dispatch)
- Up to 32 stores queued in the STQ (available for forwarding)
• Fast, selective flush of incorrect speculative instructions and results
• Specific focus on storage latency management
• Out-of-order and speculative issue of load operations
• Support for up to 8 outstanding L1 cache line misses
• Hardware initiated instruction prefetching from L2 cache
• Software initiated data stream prefetching
- Support for up to 8 active streams
• Critical word forwarding / critical sector first
• New branch processing / prediction hints added to branch instructions
• Power management
• Static power management
- Software initiated doze and nap
• Dynamic power management
- Parts of the design stop their (hardware initiated) clocks when not in use
• PowerTune
- Software initiated slow down of the processor; selectable to half of the nominal operating
frequency
General Information
October 14, 2005
Page 12 of 74
IBM [ IBM ]
