Datasheet
PowerPC 970FX RISC Microprocessor
List of Figures
Figure 1-1. PowerPC 970FX Block Diagram ................................................................................................ 15
Figure 1-2. Part Number Legend .................................................................................................................. 18
Figure 3-1. Clock Differential HSTL Signal ................................................................................................... 27
Figure 3-2. Processor-Clock Timing Relationship between PSYNC and SYSCLK ...................................... 29
Figure 3-3. Block Diagram of an SSB for a Processor Interconnect Implementation ................................... 30
Figure 3-4. Typical Implementation for a Single-Ended Line ........................................................................ 31
Figure 3-5. Differential Clock Termination Circuitry ...................................................................................... 32
Figure 3-6. Post-IAP Eye Opening ............................................................................................................... 33
Figure 3-7. Asynchronous Input Timing ........................................................................................................ 35
Figure 3-8. HRESET and BYPASS Timing Diagram .................................................................................... 38
Figure 3-9. Spread Spectrum Clock Generator Modulation Profile .............................................................. 40
Figure 3-10. JTAG Clock Input Timing Diagram ........................................................................................... 42
Figure 3-11. Test Access Port Timing Diagram ............................................................................................ 43
Figure 4-1. PowerPC 970FX Microprocessor Mechanical Package for Standard Lead DD3.0x Parts ........ 46
Figure 4-2. PowerPC 970FX Microprocessor Mechanical Package for Standard Lead, DD3.1x Parts ....... 47
Figure 4-3. PowerPC 970FX Microprocessor Bottom Dimensions for Standard Lead CBGA Package ....... 48
Figure 4-4. PowerPC 970FX Microprocessor Mechanical Package for Reduced-Lead DD3.0x Parts ........ 50
Figure 4-5. PowerPC 970FX Microprocessor Mechanical Package for Reduced-Lead DD3.1 Parts .......... 51
Figure 4-6. PowerPC 970FX Microprocessor Bottom Dimensions for Reduced-Lead CBGA Package ....... 52
Figure 4-7. PowerPC 970FX Ball Placement (Top View) ............................................................................. 53
Figure 4-8. PowerPC 970FX Ball Placement (Bottom View) ........................................................................ 54
Figure 5-1. PLL Power Supply Filter Circuit ................................................................................................. 66
Figure 5-2. Decoupling Capacitor Locations ................................................................................................ 68
Figure 5-3. PowerPC 970FX Thermal Diode Implementation ...................................................................... 76
Figure 5-4. Force Diagram for the PowerPC 970FX Package ..................................................................... 77
Version 2.5
List of Figures
Page 5 of 78
March 26, 2007
IBM [ IBM ]
